Lines Matching refs:base
75 void __iomem *base;
240 host->base + MMCI_STM32_IDMABASE0R);
242 host->base + MMCI_STM32_IDMACTRLR);
258 writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR);
259 writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR);
260 writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R);
261 writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER);
263 host->base + MMCI_STM32_IDMACTRLR);
276 writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
290 writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
352 if (!dlyb || !dlyb->base)
356 writel_relaxed(0, dlyb->base + DLYB_CR);
390 host->base + MMCIMASK0);
423 writel_relaxed(thr, host->base + MMCI_STM32_FIFOTHRR);
440 void __iomem *base = host->base;
443 mask = readl_relaxed(base + MMCIMASK0);
444 sdmmc_status = readl_relaxed(base + MMCISTATUS);
460 base + MMCIMASK0);
470 base + MMCIMASK0);
474 writel_relaxed(host->variant->busy_detect_mask, base + MMCICLEAR);
481 writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR);
491 writel_relaxed(DLYB_CR_SEN | DLYB_CR_DEN, dlyb->base + DLYB_CR);
495 writel_relaxed(cfgr, dlyb->base + DLYB_CFGR);
498 writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR);
512 ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr,
540 cr = readl_relaxed(dlyb->base + SYSCFG_DLYBSD_CR);
543 writel_relaxed(cr, dlyb->base + SYSCFG_DLYBSD_CR);
545 return readl_relaxed_poll_timeout(dlyb->base + SYSCFG_DLYBSD_SR,
556 cr = readl_relaxed(dlyb->base + SYSCFG_DLYBSD_CR);
560 writel_relaxed(cr, dlyb->base + SYSCFG_DLYBSD_CR);
562 return readl_relaxed_poll_timeout(dlyb->base + SYSCFG_DLYBSD_SR,
633 if (!dlyb || !dlyb->base)
659 writel_relaxed(MCI_STM32_VSWENDC, host->base + MMCICLEAR);
678 ret = readl_relaxed_poll_timeout(host->base + MMCISTATUS,
684 host->base + MMCICLEAR);
730 host->pwr_reg = readl_relaxed(host->base + MMCIPOWER);
740 dlyb->base = base_dlyb;