Lines Matching defs:host
10 #include <linux/mmc/host.h>
69 int (*tuning_prepare)(struct mmci_host *host);
81 static int sdmmc_idma_validate_data(struct mmci_host *host,
84 struct sdmmc_idma *idma = host->dma_priv;
85 struct device *dev = mmc_dev(host->mmc);
97 host->variant->stm32_idmabsize_align)) {
98 dev_dbg(mmc_dev(host->mmc),
106 dev_dbg(mmc_dev(host->mmc),
117 host->mmc->max_req_size,
131 static int _sdmmc_idma_prep_data(struct mmci_host *host,
134 struct sdmmc_idma *idma = host->dma_priv;
147 n_elem = dma_map_sg(mmc_dev(host->mmc),
153 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
160 static int sdmmc_idma_prep_data(struct mmci_host *host,
164 if (!next && data->host_cookie == host->next_cookie)
167 return _sdmmc_idma_prep_data(host, data);
170 static void sdmmc_idma_unprep_data(struct mmci_host *host,
173 struct sdmmc_idma *idma = host->dma_priv;
183 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
188 static int sdmmc_idma_setup(struct mmci_host *host)
191 struct device *dev = mmc_dev(host->mmc);
197 host->dma_priv = idma;
199 if (host->variant->dma_lli) {
206 host->mmc->max_segs = SDMMC_LLI_BUF_LEN /
208 host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask;
210 host->mmc->max_req_size = SZ_1M;
212 host->mmc->max_segs = 1;
213 host->mmc->max_seg_size = host->mmc->max_req_size;
216 return dma_set_max_seg_size(dev, host->mmc->max_seg_size);
219 static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl)
222 struct sdmmc_idma *idma = host->dma_priv;
224 struct mmc_data *data = host->data;
228 host->dma_in_progress = true;
230 if (!host->variant->dma_lli || data->sg_len == 1 ||
240 host->base + MMCI_STM32_IDMABASE0R);
242 host->base + MMCI_STM32_IDMACTRLR);
258 writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR);
259 writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR);
260 writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R);
261 writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER);
263 host->base + MMCI_STM32_IDMACTRLR);
268 static void sdmmc_idma_error(struct mmci_host *host)
270 struct mmc_data *data = host->data;
271 struct sdmmc_idma *idma = host->dma_priv;
273 if (!dma_inprogress(host))
276 writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
277 host->dma_in_progress = false;
281 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
285 static void sdmmc_idma_finalize(struct mmci_host *host, struct mmc_data *data)
287 if (!dma_inprogress(host))
290 writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
291 host->dma_in_progress = false;
294 sdmmc_idma_unprep_data(host, data, 0);
297 static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired)
301 if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
302 host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
311 if (desired >= host->mclk && !ddr) {
312 host->cclk = host->mclk;
314 clk = DIV_ROUND_UP(host->mclk, 2 * desired);
317 host->cclk = host->mclk / (2 * clk);
326 host->cclk = host->mclk / (2 * clk);
330 if (host->mmc->ios.power_mode == MMC_POWER_ON)
331 host->mmc->actual_clock = host->cclk;
333 host->mmc->actual_clock = 0;
335 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
337 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
341 clk |= host->clk_reg_add;
344 if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50)
347 mmci_write_clkreg(host, clk);
359 static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr)
361 struct mmc_ios ios = host->mmc->ios;
362 struct sdmmc_dlyb *dlyb = host->variant_priv;
365 pwr = host->pwr_reg_add;
372 reset_control_assert(host->rst);
374 reset_control_deassert(host->rst);
382 mmci_write_pwrreg(host, MCI_STM32_PWR_CYC | pwr);
389 writel(MCI_IRQENABLE | host->variant->start_err,
390 host->base + MMCIMASK0);
393 pwr |= host->pwr_reg & (MCI_STM32_VSWITCHEN |
401 mmci_write_pwrreg(host, MCI_PWR_OFF | pwr);
403 mmci_write_pwrreg(host, MCI_PWR_ON | pwr);
407 static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host)
411 datactrl = mmci_dctrl_blksz(host);
413 if (host->hw_revision >= 3) {
416 if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104 ||
417 host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
418 thr = ffs(min_t(unsigned int, host->data->blksz,
419 host->variant->fifosize));
423 writel_relaxed(thr, host->base + MMCI_STM32_FIFOTHRR);
426 if (host->mmc->card && mmc_card_sdio(host->mmc->card) &&
427 host->data->blocks == 1)
429 else if (host->data->stop && !host->mrq->sbc)
437 static bool sdmmc_busy_complete(struct mmci_host *host, struct mmc_command *cmd,
440 void __iomem *base = host->base;
458 if (!host->busy_status) {
459 writel_relaxed(mask | host->variant->busy_detect_mask,
461 host->busy_status = status &
468 if (host->busy_status) {
469 writel_relaxed(mask & ~host->variant->busy_detect_mask,
471 host->busy_status = 0;
474 writel_relaxed(host->variant->busy_detect_mask, base + MMCICLEAR);
503 static int sdmmc_dlyb_mp15_prepare(struct mmci_host *host)
505 struct sdmmc_dlyb *dlyb = host->variant_priv;
516 dev_warn(mmc_dev(host->mmc),
567 static int sdmmc_dlyb_mp25_prepare(struct mmci_host *host)
569 struct sdmmc_dlyb *dlyb = host->variant_priv;
576 static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode)
578 struct sdmmc_dlyb *dlyb = host->variant_priv;
585 dev_err(mmc_dev(host->mmc), "tuning config failed\n");
589 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
601 dev_err(mmc_dev(host->mmc), "no tuning point found\n");
611 dev_err(mmc_dev(host->mmc), "tuning reconfig failed\n");
615 dev_dbg(mmc_dev(host->mmc), "unit:%d max_dly:%d phase:%d\n",
623 struct mmci_host *host = mmc_priv(mmc);
624 struct sdmmc_dlyb *dlyb = host->variant_priv;
628 if ((host->mmc->ios.timing != MMC_TIMING_UHS_SDR104 &&
629 host->mmc->ios.timing != MMC_TIMING_MMC_HS200) ||
630 host->mmc->actual_clock <= 50000000)
644 clk = host->clk_reg;
647 mmci_write_clkreg(host, clk);
649 ret = dlyb->ops->tuning_prepare(host);
653 return sdmmc_dlyb_phase_tuning(host, opcode);
656 static void sdmmc_pre_sig_volt_vswitch(struct mmci_host *host)
659 writel_relaxed(MCI_STM32_VSWENDC, host->base + MMCICLEAR);
661 mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCHEN);
664 static int sdmmc_post_sig_volt_switch(struct mmci_host *host,
671 spin_lock_irqsave(&host->lock, flags);
673 host->pwr_reg & MCI_STM32_VSWITCHEN) {
674 mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH);
675 spin_unlock_irqrestore(&host->lock, flags);
678 ret = readl_relaxed_poll_timeout(host->base + MMCISTATUS,
684 host->base + MMCICLEAR);
685 spin_lock_irqsave(&host->lock, flags);
686 mmci_write_pwrreg(host, host->pwr_reg &
689 spin_unlock_irqrestore(&host->lock, flags);
723 void sdmmc_variant_init(struct mmci_host *host)
725 struct device_node *np = host->mmc->parent->of_node;
729 host->ops = &sdmmc_variant_ops;
730 host->pwr_reg = readl_relaxed(host->base + MMCIPOWER);
732 base_dlyb = devm_of_iomap(mmc_dev(host->mmc), np, 1, NULL);
736 dlyb = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dlyb), GFP_KERNEL);
746 host->variant_priv = dlyb;
747 host->mmc_ops->execute_tuning = sdmmc_execute_tuning;