Lines Matching defs:host
3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
23 #include <linux/mmc/host.h>
49 static void mmci_variant_init(struct mmci_host *host);
50 static void ux500_variant_init(struct mmci_host *host);
51 static void ux500v2_variant_init(struct mmci_host *host);
369 struct mmci_host *host = mmc_priv(mmc);
373 spin_lock_irqsave(&host->lock, flags);
374 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
376 spin_unlock_irqrestore(&host->lock, flags);
381 static void mmci_reg_delay(struct mmci_host *host)
390 if (host->cclk < 25000000)
397 * This must be called with host->lock held
399 void mmci_write_clkreg(struct mmci_host *host, u32 clk)
401 if (host->clk_reg != clk) {
402 host->clk_reg = clk;
403 writel(clk, host->base + MMCICLOCK);
408 * This must be called with host->lock held
410 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
412 if (host->pwr_reg != pwr) {
413 host->pwr_reg = pwr;
414 writel(pwr, host->base + MMCIPOWER);
419 * This must be called with host->lock held
421 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
424 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
426 if (host->datactrl_reg != datactrl) {
427 host->datactrl_reg = datactrl;
428 writel(datactrl, host->base + MMCIDATACTRL);
433 * This must be called with host->lock held
435 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
437 struct variant_data *variant = host->variant;
441 host->cclk = 0;
445 host->cclk = host->mclk;
446 } else if (desired >= host->mclk) {
450 host->cclk = host->mclk;
458 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
461 host->cclk = host->mclk / (clk + 2);
467 clk = host->mclk / (2 * desired) - 1;
470 host->cclk = host->mclk / (2 * (clk + 1));
480 host->mmc->actual_clock = host->cclk;
482 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
484 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
487 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
488 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
491 mmci_write_clkreg(host, clk);
494 static void mmci_dma_release(struct mmci_host *host)
496 if (host->ops && host->ops->dma_release)
497 host->ops->dma_release(host);
499 host->use_dma = false;
502 static void mmci_dma_setup(struct mmci_host *host)
504 if (!host->ops || !host->ops->dma_setup)
507 if (host->ops->dma_setup(host))
511 host->next_cookie = 1;
513 host->use_dma = true;
519 static int mmci_validate_data(struct mmci_host *host,
522 struct variant_data *variant = host->variant;
527 dev_err(mmc_dev(host->mmc),
532 if (host->ops && host->ops->validate_data)
533 return host->ops->validate_data(host, data);
538 static int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next)
542 if (!host->ops || !host->ops->prep_data)
545 err = host->ops->prep_data(host, data, next);
548 data->host_cookie = ++host->next_cookie < 0 ?
549 1 : host->next_cookie;
554 static void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data,
557 if (host->ops && host->ops->unprep_data)
558 host->ops->unprep_data(host, data, err);
563 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
565 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie);
567 if (host->ops && host->ops->get_next_data)
568 host->ops->get_next_data(host, data);
571 static int mmci_dma_start(struct mmci_host *host, unsigned int datactrl)
573 struct mmc_data *data = host->data;
576 if (!host->use_dma)
579 ret = mmci_prep_data(host, data, false);
583 if (!host->ops || !host->ops->dma_start)
587 dev_vdbg(mmc_dev(host->mmc),
591 ret = host->ops->dma_start(host, &datactrl);
596 mmci_write_datactrlreg(host, datactrl);
603 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
604 host->base + MMCIMASK0);
608 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
610 if (!host->use_dma)
613 if (host->ops && host->ops->dma_finalize)
614 host->ops->dma_finalize(host, data);
617 static void mmci_dma_error(struct mmci_host *host)
619 if (!host->use_dma)
622 if (host->ops && host->ops->dma_error)
623 host->ops->dma_error(host);
627 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
629 writel(0, host->base + MMCICOMMAND);
631 BUG_ON(host->data);
633 host->mrq = NULL;
634 host->cmd = NULL;
636 mmc_request_done(host->mmc, mrq);
639 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
641 void __iomem *base = host->base;
642 struct variant_data *variant = host->variant;
644 if (host->singleirq) {
656 host->mask1_reg = mask;
659 static void mmci_stop_data(struct mmci_host *host)
661 mmci_write_datactrlreg(host, 0);
662 mmci_set_mask1(host, 0);
663 host->data = NULL;
666 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
675 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
678 static u32 mmci_get_dctrl_cfg(struct mmci_host *host)
680 return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host);
683 static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host)
685 return MCI_DPSM_ENABLE | (host->data->blksz << 16);
688 static void ux500_busy_clear_mask_done(struct mmci_host *host)
690 void __iomem *base = host->base;
692 writel(host->variant->busy_detect_mask, base + MMCICLEAR);
694 ~host->variant->busy_detect_mask, base + MMCIMASK0);
695 host->busy_state = MMCI_BUSY_DONE;
696 host->busy_status = 0;
702 * host->busy_status until we know the card is not busy any more.
716 static bool ux500_busy_complete(struct mmci_host *host, struct mmc_command *cmd,
719 void __iomem *base = host->base;
724 ux500_busy_clear_mask_done(host);
732 switch (host->busy_state) {
738 * store the status in host->busy_status.
749 * host->busy_status, which is what it should be in IDLE.
751 host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND);
755 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND);
756 if (status & host->variant->busy_detect_flag) {
758 host->variant->busy_detect_mask,
760 host->busy_state = MMCI_BUSY_WAITING_FOR_START_IRQ;
761 schedule_delayed_work(&host->ux500_busy_timeout_work,
767 dev_dbg(mmc_dev(host->mmc),
769 ux500_busy_clear_mask_done(host);
784 if (status & host->variant->busy_detect_flag) {
785 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND);
786 writel(host->variant->busy_detect_mask, base + MMCICLEAR);
787 host->busy_state = MMCI_BUSY_WAITING_FOR_END_IRQ;
789 dev_dbg(mmc_dev(host->mmc),
792 cancel_delayed_work(&host->ux500_busy_timeout_work);
793 ux500_busy_clear_mask_done(host);
798 if (!(status & host->variant->busy_detect_flag)) {
799 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND);
800 writel(host->variant->busy_detect_mask, base + MMCICLEAR);
801 cancel_delayed_work(&host->ux500_busy_timeout_work);
802 ux500_busy_clear_mask_done(host);
804 dev_dbg(mmc_dev(host->mmc),
811 dev_dbg(mmc_dev(host->mmc), "fell through on state %d, CMD%02x\n",
812 host->busy_state, cmd->opcode);
817 return (host->busy_state == MMCI_BUSY_DONE);
839 int mmci_dmae_setup(struct mmci_host *host)
844 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL);
848 host->dma_priv = dmae;
850 dmae->rx_channel = dma_request_chan(mmc_dev(host->mmc), "rx");
857 dmae->tx_channel = dma_request_chan(mmc_dev(host->mmc), "tx");
860 dev_warn(mmc_dev(host->mmc),
883 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
894 if (max_seg_size < host->mmc->max_seg_size)
895 host->mmc->max_seg_size = max_seg_size;
901 if (max_seg_size < host->mmc->max_seg_size)
902 host->mmc->max_seg_size = max_seg_size;
906 mmci_dmae_release(host);
917 void mmci_dmae_release(struct mmci_host *host)
919 struct mmci_dmae_priv *dmae = host->dma_priv;
928 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
930 struct mmci_dmae_priv *dmae = host->dma_priv;
942 void mmci_dmae_error(struct mmci_host *host)
944 struct mmci_dmae_priv *dmae = host->dma_priv;
946 if (!dma_inprogress(host))
949 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
951 host->dma_in_progress = false;
954 host->data->host_cookie = 0;
956 mmci_dma_unmap(host, host->data);
959 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data)
961 struct mmci_dmae_priv *dmae = host->dma_priv;
965 if (!dma_inprogress(host))
970 status = readl(host->base + MMCISTATUS);
983 mmci_dma_error(host);
987 mmci_dma_unmap(host, data);
995 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
996 mmci_dma_release(host);
999 host->dma_in_progress = false;
1005 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
1009 struct mmci_dmae_priv *dmae = host->dma_priv;
1010 struct variant_data *variant = host->variant;
1012 .src_addr = host->phybase + MMCIFIFO,
1013 .dst_addr = host->phybase + MMCIFIFO,
1051 if (host->variant->dma_power_of_2 && !is_power_of_2(data->blksz))
1060 if (host->variant->qcom_dml)
1080 int mmci_dmae_prep_data(struct mmci_host *host,
1084 struct mmci_dmae_priv *dmae = host->dma_priv;
1087 if (!host->use_dma)
1091 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc);
1097 return _mmci_dmae_prep_data(host, data, &dmae->cur,
1101 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl)
1103 struct mmci_dmae_priv *dmae = host->dma_priv;
1106 host->dma_in_progress = true;
1109 host->dma_in_progress = false;
1119 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data)
1121 struct mmci_dmae_priv *dmae = host->dma_priv;
1124 if (!host->use_dma)
1135 void mmci_dmae_unprep_data(struct mmci_host *host,
1139 struct mmci_dmae_priv *dmae = host->dma_priv;
1141 if (!host->use_dma)
1144 mmci_dma_unmap(host, data);
1159 host->dma_in_progress = false;
1185 static void mmci_variant_init(struct mmci_host *host)
1187 host->ops = &mmci_variant_ops;
1190 static void ux500_variant_init(struct mmci_host *host)
1192 host->ops = &mmci_variant_ops;
1193 host->ops->busy_complete = ux500_busy_complete;
1196 static void ux500v2_variant_init(struct mmci_host *host)
1198 host->ops = &mmci_variant_ops;
1199 host->ops->busy_complete = ux500_busy_complete;
1200 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg;
1205 struct mmci_host *host = mmc_priv(mmc);
1213 if (mmci_validate_data(host, data))
1216 mmci_prep_data(host, data, true);
1222 struct mmci_host *host = mmc_priv(mmc);
1228 mmci_unprep_data(host, data, err);
1231 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
1233 struct variant_data *variant = host->variant;
1238 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
1241 host->data = data;
1242 host->size = data->blksz * data->blocks;
1245 clks = (unsigned long long)data->timeout_ns * host->cclk;
1250 base = host->base;
1252 writel(host->size, base + MMCIDATALENGTH);
1254 datactrl = host->ops->get_datactrl_cfg(host);
1255 datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0;
1257 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
1269 (host->size < 8 ||
1270 (host->size <= 8 && host->mclk > 50000000)))
1271 clk = host->clk_reg & ~variant->clkreg_enable;
1273 clk = host->clk_reg | variant->clkreg_enable;
1275 mmci_write_clkreg(host, clk);
1278 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
1279 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
1286 if (!mmci_dma_start(host, datactrl))
1290 mmci_init_sg(host, data);
1300 if (host->size < variant->fifohalfsize)
1310 mmci_write_datactrlreg(host, datactrl);
1312 mmci_set_mask1(host, irqmask);
1316 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
1318 void __iomem *base = host->base;
1322 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
1325 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) {
1327 mmci_reg_delay(host);
1330 if (host->variant->cmdreg_stop &&
1332 c |= host->variant->cmdreg_stop;
1334 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable;
1337 c |= host->variant->cmdreg_lrsp_crc;
1339 c |= host->variant->cmdreg_srsp_crc;
1341 c |= host->variant->cmdreg_srsp;
1344 host->busy_status = 0;
1345 host->busy_state = MMCI_BUSY_DONE;
1351 if (busy_resp && host->variant->busy_timeout) {
1352 if (cmd->busy_timeout > host->mmc->max_busy_timeout)
1353 clks = (unsigned long long)host->mmc->max_busy_timeout * host->cclk;
1355 clks = (unsigned long long)cmd->busy_timeout * host->cclk;
1358 writel_relaxed(clks, host->base + MMCIDATATIMER);
1361 if (host->ops->pre_sig_volt_switch && cmd->opcode == SD_SWITCH_VOLTAGE)
1362 host->ops->pre_sig_volt_switch(host);
1368 c |= host->variant->data_cmd_enable;
1370 host->cmd = cmd;
1376 static void mmci_stop_command(struct mmci_host *host)
1378 host->stop_abort.error = 0;
1379 mmci_start_command(host, &host->stop_abort, 0);
1383 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
1393 status_err = status & (host->variant->start_err |
1401 mmci_dma_error(host);
1406 * on the MMC bus, not on the host side. On reads, this
1410 if (!host->variant->datacnt_useless) {
1411 remain = readl(host->base + MMCIDATACNT);
1417 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
1430 if (success > host->variant->fifosize)
1431 success -= host->variant->fifosize;
1440 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
1443 mmci_dma_finalize(host, data);
1445 mmci_stop_data(host);
1452 if (host->variant->cmdreg_stop && data->error)
1453 mmci_stop_command(host);
1455 mmci_request_end(host, data->mrq);
1456 } else if (host->mrq->sbc && !data->error) {
1457 mmci_request_end(host, data->mrq);
1459 mmci_start_command(host, data->stop, 0);
1465 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
1469 void __iomem *base = host->base;
1475 sbc = (cmd == host->mrq->sbc);
1483 if (host->variant->busy_timeout && busy_resp)
1486 if (!((status | host->busy_status) &
1491 if (busy_resp && host->variant->busy_detect)
1492 if (!host->ops->busy_complete(host, cmd, status, err_msk))
1495 host->cmd = NULL;
1501 } else if (host->variant->busy_timeout && busy_resp &&
1508 host->irq_action = IRQ_WAKE_THREAD;
1517 if (host->data) {
1519 mmci_dma_error(host);
1521 mmci_stop_data(host);
1522 if (host->variant->cmdreg_stop && cmd->error) {
1523 mmci_stop_command(host);
1528 if (host->irq_action != IRQ_WAKE_THREAD)
1529 mmci_request_end(host, host->mrq);
1532 mmci_start_command(host, host->mrq->cmd, 0);
1533 } else if (!host->variant->datactrl_first &&
1535 mmci_start_data(host, cmd->data);
1539 static char *ux500_state_str(struct mmci_host *host)
1541 switch (host->busy_state) {
1560 struct mmci_host *host = container_of(work, struct mmci_host,
1565 spin_lock_irqsave(&host->lock, flags);
1567 if (host->cmd) {
1569 status = readl(host->base + MMCISTATUS);
1570 if (status & host->variant->busy_detect_flag) {
1572 dev_err(mmc_dev(host->mmc),
1574 ux500_state_str(host), host->cmd->opcode);
1576 dev_err(mmc_dev(host->mmc),
1578 ux500_state_str(host), host->cmd->opcode);
1581 mmci_cmd_irq(host, host->cmd, status);
1584 spin_unlock_irqrestore(&host->lock, flags);
1587 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1589 return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1592 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1599 return host->variant->fifohalfsize;
1606 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1608 void __iomem *base = host->base;
1610 u32 status = readl(host->base + MMCISTATUS);
1611 int host_remain = host->size;
1614 int count = host->get_rx_fifocnt(host, status, host_remain);
1654 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1656 struct variant_data *variant = host->variant;
1657 void __iomem *base = host->base;
1694 struct mmci_host *host = dev_id;
1695 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1696 struct variant_data *variant = host->variant;
1697 void __iomem *base = host->base;
1702 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1726 len = mmci_pio_read(host, buffer, remain);
1728 len = mmci_pio_write(host, buffer, remain, status);
1732 host->size -= len;
1747 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1748 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1756 if (host->size == 0) {
1757 mmci_set_mask1(host, 0);
1769 struct mmci_host *host = dev_id;
1772 spin_lock(&host->lock);
1773 host->irq_action = IRQ_HANDLED;
1776 status = readl(host->base + MMCISTATUS);
1780 if (host->singleirq) {
1781 if (status & host->mask1_reg)
1784 status &= ~host->variant->irq_pio_mask;
1791 status &= readl(host->base + MMCIMASK0);
1792 if (host->variant->busy_detect)
1793 writel(status & ~host->variant->busy_detect_mask,
1794 host->base + MMCICLEAR);
1796 writel(status, host->base + MMCICLEAR);
1798 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1800 if (host->variant->reversed_irq_handling) {
1801 mmci_data_irq(host, host->data, status);
1802 mmci_cmd_irq(host, host->cmd, status);
1804 mmci_cmd_irq(host, host->cmd, status);
1805 mmci_data_irq(host, host->data, status);
1812 if (host->variant->busy_detect_flag)
1813 status &= ~host->variant->busy_detect_flag;
1817 spin_unlock(&host->lock);
1819 return host->irq_action;
1830 struct mmci_host *host = dev_id;
1833 if (host->rst) {
1834 reset_control_assert(host->rst);
1836 reset_control_deassert(host->rst);
1839 spin_lock_irqsave(&host->lock, flags);
1840 writel(host->clk_reg, host->base + MMCICLOCK);
1841 writel(host->pwr_reg, host->base + MMCIPOWER);
1842 writel(MCI_IRQENABLE | host->variant->start_err,
1843 host->base + MMCIMASK0);
1845 host->irq_action = IRQ_HANDLED;
1846 mmci_request_end(host, host->mrq);
1847 spin_unlock_irqrestore(&host->lock, flags);
1849 return host->irq_action;
1854 struct mmci_host *host = mmc_priv(mmc);
1857 WARN_ON(host->mrq != NULL);
1859 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1865 spin_lock_irqsave(&host->lock, flags);
1867 host->mrq = mrq;
1870 mmci_get_next_data(host, mrq->data);
1873 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ))
1874 mmci_start_data(host, mrq->data);
1877 mmci_start_command(host, mrq->sbc, 0);
1879 mmci_start_command(host, mrq->cmd, 0);
1881 spin_unlock_irqrestore(&host->lock, flags);
1886 struct mmci_host *host = mmc_priv(mmc);
1889 if (!host->variant->busy_detect)
1892 if (host->variant->busy_timeout && mmc->actual_clock)
1901 struct mmci_host *host = mmc_priv(mmc);
1902 struct variant_data *variant = host->variant;
1912 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1914 host->vqmmc_enabled = false;
1931 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1937 host->vqmmc_enabled = true;
1950 pwr |= host->pwr_reg_add;
1969 pinctrl_select_state(host->pinctrl, host->pins_opendrain);
1981 if (host->variant->explicit_mclk_control &&
1982 ios->clock != host->clock_cache) {
1983 ret = clk_set_rate(host->clk, ios->clock);
1985 dev_err(mmc_dev(host->mmc),
1988 host->mclk = clk_get_rate(host->clk);
1990 host->clock_cache = ios->clock;
1992 spin_lock_irqsave(&host->lock, flags);
1994 if (host->ops && host->ops->set_clkreg)
1995 host->ops->set_clkreg(host, ios->clock);
1997 mmci_set_clkreg(host, ios->clock);
2001 if (host->ops && host->ops->set_pwrreg)
2002 host->ops->set_pwrreg(host, pwr);
2004 mmci_write_pwrreg(host, pwr);
2006 mmci_reg_delay(host);
2008 spin_unlock_irqrestore(&host->lock, flags);
2013 struct mmci_host *host = mmc_priv(mmc);
2014 struct mmci_platform_data *plat = host->plat;
2021 status = plat->status(mmc_dev(host->mmc));
2028 struct mmci_host *host = mmc_priv(mmc);
2033 if (!ret && host->ops && host->ops->post_sig_volt_switch)
2034 ret = host->ops->post_sig_volt_switch(host, ios);
2057 struct mmci_host *host = mmc_priv(mmc);
2067 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN;
2098 host->clk_reg_add &= ~MCI_STM32_CLK_SELCKIN;
2115 struct mmci_host *host = mmc_priv(mmc);
2122 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
2124 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
2126 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
2128 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
2130 host->pwr_reg_add |= MCI_ST_CMDDIREN;
2132 host->pwr_reg_add |= MCI_ST_FBCLKEN;
2134 host->pwr_reg_add |= MCI_STM32_DIRPOL;
2136 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE;
2154 struct mmci_host *host;
2174 host = mmc_priv(mmc);
2175 host->mmc = mmc;
2176 host->mmc_ops = &mmci_ops;
2188 host->pinctrl = devm_pinctrl_get(&dev->dev);
2189 if (IS_ERR(host->pinctrl)) {
2191 ret = PTR_ERR(host->pinctrl);
2195 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl,
2197 if (IS_ERR(host->pins_opendrain)) {
2199 ret = PTR_ERR(host->pins_opendrain);
2204 host->hw_designer = amba_manf(dev);
2205 host->hw_revision = amba_rev(dev);
2206 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
2207 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
2209 host->clk = devm_clk_get(&dev->dev, NULL);
2210 if (IS_ERR(host->clk)) {
2211 ret = PTR_ERR(host->clk);
2215 ret = clk_prepare_enable(host->clk);
2220 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
2222 host->get_rx_fifocnt = mmci_get_rx_fifocnt;
2224 host->plat = plat;
2225 host->variant = variant;
2226 host->mclk = clk_get_rate(host->clk);
2232 if (host->mclk > variant->f_max) {
2233 ret = clk_set_rate(host->clk, variant->f_max);
2236 host->mclk = clk_get_rate(host->clk);
2238 host->mclk);
2241 host->phybase = dev->res.start;
2242 host->base = devm_ioremap_resource(&dev->dev, &dev->res);
2243 if (IS_ERR(host->base)) {
2244 ret = PTR_ERR(host->base);
2249 variant->init(host);
2258 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
2260 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046);
2262 mmc->f_min = clk_round_rate(host->clk, 100000);
2264 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
2274 min(host->mclk, mmc->f_max);
2277 fmax : min(host->mclk, fmax);
2282 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
2283 if (IS_ERR(host->rst)) {
2284 ret = PTR_ERR(host->rst);
2287 ret = reset_control_deassert(host->rst);
2314 mmci_write_datactrlreg(host,
2315 host->variant->busy_dpsm_flag);
2324 host->stop_abort.opcode = MMC_STOP_TRANSMISSION;
2325 host->stop_abort.arg = 0;
2326 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC;
2360 spin_lock_init(&host->lock);
2362 writel(0, host->base + MMCIMASK0);
2365 writel(0, host->base + MMCIMASK1);
2367 writel(0xfff, host->base + MMCICLEAR);
2388 DRIVER_NAME " (cmd)", host);
2393 host->singleirq = true;
2396 IRQF_SHARED, DRIVER_NAME " (pio)", host);
2401 if (host->variant->busy_detect)
2402 INIT_DELAYED_WORK(&host->ux500_busy_timeout_work,
2405 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0);
2414 mmci_dma_setup(host);
2427 clk_disable_unprepare(host->clk);
2438 struct mmci_host *host = mmc_priv(mmc);
2439 struct variant_data *variant = host->variant;
2449 writel(0, host->base + MMCIMASK0);
2452 writel(0, host->base + MMCIMASK1);
2454 writel(0, host->base + MMCICOMMAND);
2455 writel(0, host->base + MMCIDATACTRL);
2457 mmci_dma_release(host);
2458 clk_disable_unprepare(host->clk);
2464 static void mmci_save(struct mmci_host *host)
2468 spin_lock_irqsave(&host->lock, flags);
2470 writel(0, host->base + MMCIMASK0);
2471 if (host->variant->pwrreg_nopower) {
2472 writel(0, host->base + MMCIDATACTRL);
2473 writel(0, host->base + MMCIPOWER);
2474 writel(0, host->base + MMCICLOCK);
2476 mmci_reg_delay(host);
2478 spin_unlock_irqrestore(&host->lock, flags);
2481 static void mmci_restore(struct mmci_host *host)
2485 spin_lock_irqsave(&host->lock, flags);
2487 if (host->variant->pwrreg_nopower) {
2488 writel(host->clk_reg, host->base + MMCICLOCK);
2489 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
2490 writel(host->pwr_reg, host->base + MMCIPOWER);
2492 writel(MCI_IRQENABLE | host->variant->start_err,
2493 host->base + MMCIMASK0);
2494 mmci_reg_delay(host);
2496 spin_unlock_irqrestore(&host->lock, flags);
2505 struct mmci_host *host = mmc_priv(mmc);
2507 mmci_save(host);
2508 clk_disable_unprepare(host->clk);
2520 struct mmci_host *host = mmc_priv(mmc);
2521 clk_prepare_enable(host->clk);
2522 mmci_restore(host);