Lines Matching refs:host
31 #include <linux/mmc/host.h>
118 spin_lock_bh(&slot->host->lock);
144 spin_unlock_bh(&slot->host->lock);
152 struct dw_mci *host = s->private;
154 pm_runtime_get_sync(host->dev);
156 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
157 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
158 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
159 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
160 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
161 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
163 pm_runtime_put_autosuspend(host->dev);
172 struct dw_mci *host = slot->host;
179 debugfs_create_file("regs", S_IRUSR, root, host, &dw_mci_regs_fops);
181 debugfs_create_u32("state", S_IRUSR, root, &host->state);
183 &host->pending_events);
185 &host->completed_events);
187 fault_create_debugfs_attr("fail_data_crc", root, &host->fail_data_crc);
192 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
196 ctrl = mci_readl(host, CTRL);
198 mci_writel(host, CTRL, ctrl);
201 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
204 dev_err(host->dev,
213 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
227 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
231 dev_err(host->dev, "Busy; trying anyway\n");
237 struct dw_mci *host = slot->host;
240 mci_writel(host, CMDARG, arg);
242 dw_mci_wait_while_busy(host, cmd);
243 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
245 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
256 struct dw_mci *host = slot->host;
278 WARN_ON(slot->host->state != STATE_SENDING_CMD);
279 slot->host->state = STATE_SENDING_CMD11;
292 clk_en_a = mci_readl(host, CLKENA);
294 mci_writel(host, CLKENA, clk_en_a);
321 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
329 stop = &host->stop_abort;
354 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
360 static inline void dw_mci_set_cto(struct dw_mci *host)
367 cto_clks = mci_readl(host, TMOUT) & 0xff;
368 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
373 host->bus_hz);
391 spin_lock_irqsave(&host->irq_lock, irqflags);
392 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
393 mod_timer(&host->cto_timer,
395 spin_unlock_irqrestore(&host->irq_lock, irqflags);
398 static void dw_mci_start_command(struct dw_mci *host,
401 host->cmd = cmd;
402 dev_vdbg(host->dev,
406 mci_writel(host, CMDARG, cmd->arg);
408 dw_mci_wait_while_busy(host, cmd_flags);
410 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
414 dw_mci_set_cto(host);
417 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
419 struct mmc_command *stop = &host->stop_abort;
421 dw_mci_start_command(host, stop, host->stop_cmdr);
425 static void dw_mci_stop_dma(struct dw_mci *host)
427 if (host->using_dma) {
428 host->dma_ops->stop(host);
429 host->dma_ops->cleanup(host);
433 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
436 static void dw_mci_dma_cleanup(struct dw_mci *host)
438 struct mmc_data *data = host->data;
441 dma_unmap_sg(host->dev,
449 static void dw_mci_idmac_reset(struct dw_mci *host)
451 u32 bmod = mci_readl(host, BMOD);
454 mci_writel(host, BMOD, bmod);
457 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
462 temp = mci_readl(host, CTRL);
465 mci_writel(host, CTRL, temp);
468 temp = mci_readl(host, BMOD);
471 mci_writel(host, BMOD, temp);
476 struct dw_mci *host = arg;
477 struct mmc_data *data = host->data;
479 dev_vdbg(host->dev, "DMA complete\n");
481 if ((host->use_dma == TRANS_MODE_EDMAC) &&
484 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
489 host->dma_ops->cleanup(host);
496 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
497 tasklet_schedule(&host->tasklet);
501 static int dw_mci_idmac_init(struct dw_mci *host)
505 if (host->dma_64bit_address == 1) {
508 host->ring_size =
512 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
514 p->des6 = (host->sg_dma +
518 p->des7 = (u64)(host->sg_dma +
529 p->des6 = host->sg_dma & 0xffffffff;
530 p->des7 = (u64)host->sg_dma >> 32;
536 host->ring_size =
540 for (i = 0, p = host->sg_cpu;
541 i < host->ring_size - 1;
543 p->des3 = cpu_to_le32(host->sg_dma +
550 p->des3 = cpu_to_le32(host->sg_dma);
554 dw_mci_idmac_reset(host);
556 if (host->dma_64bit_address == 1) {
558 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
559 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
563 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
564 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
568 mci_writel(host, IDSTS, IDMAC_INT_CLR);
569 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
573 mci_writel(host, DBADDR, host->sg_dma);
579 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
588 desc_first = desc_last = desc = host->sg_cpu;
644 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
645 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
646 dw_mci_idmac_init(host);
651 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
660 desc_first = desc_last = desc = host->sg_cpu;
718 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
719 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
720 dw_mci_idmac_init(host);
724 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
729 if (host->dma_64bit_address == 1)
730 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
732 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
741 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
742 dw_mci_idmac_reset(host);
745 temp = mci_readl(host, CTRL);
747 mci_writel(host, CTRL, temp);
753 temp = mci_readl(host, BMOD);
755 mci_writel(host, BMOD, temp);
758 mci_writel(host, PLDMND, 1);
772 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
774 dmaengine_terminate_async(host->dms->ch);
777 static int dw_mci_edmac_start_dma(struct dw_mci *host,
782 struct scatterlist *sgl = host->data->sg;
784 u32 sg_elems = host->data->sg_len;
786 u32 fifo_offset = host->fifo_reg - host->regs;
791 cfg.dst_addr = host->phy_regs + fifo_offset;
797 fifoth_val = mci_readl(host, FIFOTH);
801 if (host->data->flags & MMC_DATA_WRITE)
806 ret = dmaengine_slave_config(host->dms->ch, &cfg);
808 dev_err(host->dev, "Failed to config edmac.\n");
812 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
816 dev_err(host->dev, "Can't prepare slave sg.\n");
822 desc->callback_param = (void *)host;
826 if (host->data->flags & MMC_DATA_WRITE)
827 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
830 dma_async_issue_pending(host->dms->ch);
835 static int dw_mci_edmac_init(struct dw_mci *host)
838 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
839 if (!host->dms)
842 host->dms->ch = dma_request_chan(host->dev, "rx-tx");
843 if (IS_ERR(host->dms->ch)) {
844 int ret = PTR_ERR(host->dms->ch);
846 dev_err(host->dev, "Failed to get external DMA channel.\n");
847 kfree(host->dms);
848 host->dms = NULL;
855 static void dw_mci_edmac_exit(struct dw_mci *host)
857 if (host->dms) {
858 if (host->dms->ch) {
859 dma_release_channel(host->dms->ch);
860 host->dms->ch = NULL;
862 kfree(host->dms);
863 host->dms = NULL;
876 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
902 sg_len = dma_map_sg(host->dev,
920 if (!slot->host->use_dma || !data)
926 if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
938 if (!slot->host->use_dma || !data)
942 dma_unmap_sg(slot->host->dev,
953 struct dw_mci *host = slot->host;
976 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
979 spin_lock_bh(&host->lock);
985 spin_unlock_bh(&host->lock);
990 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
994 u32 fifo_width = 1 << host->data_shift;
1000 if (!host->use_dma)
1003 tx_wmark = (host->fifo_depth) / 2;
1004 tx_wmark_invers = host->fifo_depth - tx_wmark;
1027 mci_writel(host, FIFOTH, fifoth_val);
1030 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
1041 if (host->verid < DW_MMC_240A ||
1042 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1050 host->timing != MMC_TIMING_MMC_HS400)
1058 if (host->timing != MMC_TIMING_MMC_HS200 &&
1059 host->timing != MMC_TIMING_UHS_SDR104 &&
1060 host->timing != MMC_TIMING_MMC_HS400)
1063 blksz_depth = blksz / (1 << host->data_shift);
1064 fifo_depth = host->fifo_depth;
1075 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1079 mci_writel(host, CDTHRCTL, 0);
1082 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1088 host->using_dma = 0;
1091 if (!host->use_dma)
1094 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1096 host->dma_ops->stop(host);
1100 host->using_dma = 1;
1102 if (host->use_dma == TRANS_MODE_IDMAC)
1103 dev_vdbg(host->dev,
1105 (unsigned long)host->sg_cpu,
1106 (unsigned long)host->sg_dma,
1114 if (host->prev_blksz != data->blksz)
1115 dw_mci_adjust_fifoth(host, data);
1118 temp = mci_readl(host, CTRL);
1120 mci_writel(host, CTRL, temp);
1123 spin_lock_irqsave(&host->irq_lock, irqflags);
1124 temp = mci_readl(host, INTMASK);
1126 mci_writel(host, INTMASK, temp);
1127 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1129 if (host->dma_ops->start(host, sg_len)) {
1130 host->dma_ops->stop(host);
1132 dev_dbg(host->dev,
1141 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1149 WARN_ON(host->data);
1150 host->sg = NULL;
1151 host->data = data;
1154 host->dir_status = DW_MCI_RECV_STATUS;
1156 host->dir_status = DW_MCI_SEND_STATUS;
1158 dw_mci_ctrl_thld(host, data);
1160 if (dw_mci_submit_data_dma(host, data)) {
1161 if (host->data->flags & MMC_DATA_READ)
1166 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1167 host->sg = data->sg;
1168 host->part_buf_start = 0;
1169 host->part_buf_count = 0;
1171 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1173 spin_lock_irqsave(&host->irq_lock, irqflags);
1174 temp = mci_readl(host, INTMASK);
1176 mci_writel(host, INTMASK, temp);
1177 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1179 temp = mci_readl(host, CTRL);
1181 mci_writel(host, CTRL, temp);
1189 if (host->wm_aligned)
1190 dw_mci_adjust_fifoth(host, data);
1192 mci_writel(host, FIFOTH, host->fifoth_val);
1193 host->prev_blksz = 0;
1200 host->prev_blksz = data->blksz;
1206 struct dw_mci *host = slot->host;
1213 if (host->state == STATE_WAITING_CMD11_DONE)
1219 mci_writel(host, CLKENA, 0);
1221 } else if (clock != host->current_speed || force_clkinit) {
1222 div = host->bus_hz / clock;
1223 if (host->bus_hz % clock && host->bus_hz > clock)
1230 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1239 slot->id, host->bus_hz, clock,
1240 div ? ((host->bus_hz / div) >> 1) :
1241 host->bus_hz, div);
1253 mci_writel(host, CLKENA, 0);
1254 mci_writel(host, CLKSRC, 0);
1260 mci_writel(host, CLKDIV, div);
1269 mci_writel(host, CLKENA, clk_en_a);
1276 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) :
1277 host->bus_hz;
1280 host->current_speed = clock;
1283 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1286 static void dw_mci_set_data_timeout(struct dw_mci *host,
1289 const struct dw_mci_drv_data *drv_data = host->drv_data;
1294 return drv_data->set_data_timeout(host, timeout_ns);
1296 clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2;
1300 tmp = DIV_ROUND_UP_ULL((u64)timeout_ns * host->bus_hz, NSEC_PER_SEC);
1312 mci_writel(host, TMOUT, tmout);
1313 dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: %#08x",
1317 static void __dw_mci_start_request(struct dw_mci *host,
1327 host->mrq = mrq;
1329 host->pending_events = 0;
1330 host->completed_events = 0;
1331 host->cmd_status = 0;
1332 host->data_status = 0;
1333 host->dir_status = 0;
1337 dw_mci_set_data_timeout(host, data->timeout_ns);
1338 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1339 mci_writel(host, BLKSIZ, data->blksz);
1349 dw_mci_submit_data(host, data);
1353 dw_mci_start_command(host, cmd, cmdflags);
1368 spin_lock_irqsave(&host->irq_lock, irqflags);
1369 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1370 mod_timer(&host->cmd11_timer,
1372 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1375 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1378 static void dw_mci_start_request(struct dw_mci *host,
1385 __dw_mci_start_request(host, slot, cmd);
1388 /* must be called with host->lock held */
1389 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1393 host->state);
1397 if (host->state == STATE_WAITING_CMD11_DONE) {
1405 host->state = STATE_IDLE;
1408 if (host->state == STATE_IDLE) {
1409 host->state = STATE_SENDING_CMD;
1410 dw_mci_start_request(host, slot);
1412 list_add_tail(&slot->queue_node, &host->queue);
1419 struct dw_mci *host = slot->host;
1435 spin_lock_bh(&host->lock);
1437 dw_mci_queue_request(host, slot, mrq);
1439 spin_unlock_bh(&host->lock);
1445 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1461 regs = mci_readl(slot->host, UHS_REG);
1471 mci_writel(slot->host, UHS_REG, regs);
1472 slot->host->timing = ios->timing;
1481 drv_data->set_ios(slot->host, ios);
1489 dev_err(slot->host->dev,
1496 regs = mci_readl(slot->host, PWREN);
1498 mci_writel(slot->host, PWREN, regs);
1501 if (!slot->host->vqmmc_enabled) {
1505 dev_err(slot->host->dev,
1508 slot->host->vqmmc_enabled = true;
1512 slot->host->vqmmc_enabled = true;
1516 dw_mci_ctrl_reset(slot->host,
1531 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1533 slot->host->vqmmc_enabled = false;
1535 regs = mci_readl(slot->host, PWREN);
1537 mci_writel(slot->host, PWREN, regs);
1543 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1544 slot->host->state = STATE_IDLE;
1556 status = mci_readl(slot->host, STATUS);
1564 struct dw_mci *host = slot->host;
1565 const struct dw_mci_drv_data *drv_data = host->drv_data;
1578 uhs = mci_readl(host, UHS_REG);
1593 mci_writel(host, UHS_REG, uhs);
1609 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1620 struct dw_mci *host = slot->host;
1623 if (host->use_dma == TRANS_MODE_IDMAC)
1624 dw_mci_idmac_reset(host);
1626 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1636 reset = mci_readl(host, RST_N);
1638 mci_writel(host, RST_N, reset);
1641 mci_writel(host, RST_N, reset);
1647 struct dw_mci *host = slot->host;
1658 clk_en_a_old = mci_readl(host, CLKENA);
1668 mci_writel(host, CLKENA, clk_en_a);
1676 struct dw_mci *host = slot->host;
1680 spin_lock_irqsave(&host->irq_lock, irqflags);
1683 int_mask = mci_readl(host, INTMASK);
1688 mci_writel(host, INTMASK, int_mask);
1690 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1696 struct dw_mci *host = slot->host;
1703 pm_runtime_get_noresume(host->dev);
1705 pm_runtime_put_noidle(host->dev);
1718 struct dw_mci *host = slot->host;
1719 const struct dw_mci_drv_data *drv_data = host->drv_data;
1731 struct dw_mci *host = slot->host;
1732 const struct dw_mci_drv_data *drv_data = host->drv_data;
1735 return drv_data->prepare_hs400_tuning(host, ios);
1740 static bool dw_mci_reset(struct dw_mci *host)
1750 if (host->sg) {
1751 sg_miter_stop(&host->sg_miter);
1752 host->sg = NULL;
1755 if (host->use_dma)
1758 if (dw_mci_ctrl_reset(host, flags)) {
1763 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1765 if (!host->use_dma) {
1771 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1775 dev_err(host->dev,
1782 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1786 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1787 dev_err(host->dev,
1794 if (host->use_dma == TRANS_MODE_IDMAC)
1796 dw_mci_idmac_init(host);
1802 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
1826 struct dw_mci *host = container_of(t, struct dw_mci, fault_timer);
1829 spin_lock_irqsave(&host->irq_lock, flags);
1835 if (!host->data_status) {
1836 host->data_status = SDMMC_INT_DCRC;
1837 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1838 tasklet_schedule(&host->tasklet);
1841 spin_unlock_irqrestore(&host->irq_lock, flags);
1846 static void dw_mci_start_fault_timer(struct dw_mci *host)
1848 struct mmc_data *data = host->data;
1853 if (!should_fail(&host->fail_data_crc, 1))
1859 hrtimer_start(&host->fault_timer,
1864 static void dw_mci_stop_fault_timer(struct dw_mci *host)
1866 hrtimer_cancel(&host->fault_timer);
1869 static void dw_mci_init_fault(struct dw_mci *host)
1871 host->fail_data_crc = (struct fault_attr) FAULT_ATTR_INITIALIZER;
1873 hrtimer_init(&host->fault_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1874 host->fault_timer.function = dw_mci_fault_timer;
1877 static void dw_mci_init_fault(struct dw_mci *host)
1881 static void dw_mci_start_fault_timer(struct dw_mci *host)
1885 static void dw_mci_stop_fault_timer(struct dw_mci *host)
1890 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1891 __releases(&host->lock)
1892 __acquires(&host->lock)
1895 struct mmc_host *prev_mmc = host->slot->mmc;
1897 WARN_ON(host->cmd || host->data);
1899 host->slot->mrq = NULL;
1900 host->mrq = NULL;
1901 if (!list_empty(&host->queue)) {
1902 slot = list_entry(host->queue.next,
1905 dev_vdbg(host->dev, "list not empty: %s is next\n",
1907 host->state = STATE_SENDING_CMD;
1908 dw_mci_start_request(host, slot);
1910 dev_vdbg(host->dev, "list empty\n");
1912 if (host->state == STATE_SENDING_CMD11)
1913 host->state = STATE_WAITING_CMD11_DONE;
1915 host->state = STATE_IDLE;
1918 spin_unlock(&host->lock);
1920 spin_lock(&host->lock);
1923 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1925 u32 status = host->cmd_status;
1927 host->cmd_status = 0;
1932 cmd->resp[3] = mci_readl(host, RESP0);
1933 cmd->resp[2] = mci_readl(host, RESP1);
1934 cmd->resp[1] = mci_readl(host, RESP2);
1935 cmd->resp[0] = mci_readl(host, RESP3);
1937 cmd->resp[0] = mci_readl(host, RESP0);
1956 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1958 u32 status = host->data_status;
1966 if (host->dir_status ==
1975 } else if (host->dir_status ==
1984 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1990 dw_mci_reset(host);
1999 static void dw_mci_set_drto(struct dw_mci *host)
2001 const struct dw_mci_drv_data *drv_data = host->drv_data;
2008 drto_clks = drv_data->get_drto_clks(host);
2010 drto_clks = mci_readl(host, TMOUT) >> 8;
2011 drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
2016 host->bus_hz);
2018 dev_dbg(host->dev, "drto_ms: %u\n", drto_ms);
2023 spin_lock_irqsave(&host->irq_lock, irqflags);
2024 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
2025 mod_timer(&host->dto_timer,
2027 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2030 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
2032 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
2042 WARN_ON(del_timer_sync(&host->cto_timer));
2043 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2048 static bool dw_mci_clear_pending_data_complete(struct dw_mci *host)
2050 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
2054 WARN_ON(del_timer_sync(&host->dto_timer));
2055 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2062 struct dw_mci *host = from_tasklet(host, t, tasklet);
2070 spin_lock(&host->lock);
2072 state = host->state;
2073 data = host->data;
2074 mrq = host->mrq;
2086 if (!dw_mci_clear_pending_cmd_complete(host))
2089 cmd = host->cmd;
2090 host->cmd = NULL;
2091 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2092 err = dw_mci_command_complete(host, cmd);
2094 __dw_mci_start_request(host, host->slot,
2122 host->dir_status == DW_MCI_RECV_STATUS) {
2127 send_stop_abort(host, data);
2128 dw_mci_stop_dma(host);
2134 dw_mci_request_end(host, mrq);
2151 &host->pending_events)) {
2152 if (!(host->data_status & (SDMMC_INT_DRTO |
2154 send_stop_abort(host, data);
2155 dw_mci_stop_dma(host);
2161 &host->pending_events)) {
2166 if (host->dir_status == DW_MCI_RECV_STATUS)
2167 dw_mci_set_drto(host);
2171 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2187 &host->pending_events)) {
2188 if (!(host->data_status & (SDMMC_INT_DRTO |
2190 send_stop_abort(host, data);
2191 dw_mci_stop_dma(host);
2200 if (!dw_mci_clear_pending_data_complete(host)) {
2206 if (host->dir_status == DW_MCI_RECV_STATUS)
2207 dw_mci_set_drto(host);
2211 dw_mci_stop_fault_timer(host);
2212 host->data = NULL;
2213 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2214 err = dw_mci_data_complete(host, data);
2220 dw_mci_request_end(host, mrq);
2226 send_stop_abort(host, data);
2238 &host->pending_events)) {
2239 host->cmd = NULL;
2240 dw_mci_request_end(host, mrq);
2254 if (!dw_mci_clear_pending_cmd_complete(host))
2259 dw_mci_reset(host);
2261 dw_mci_stop_fault_timer(host);
2262 host->cmd = NULL;
2263 host->data = NULL;
2266 dw_mci_command_complete(host, mrq->stop);
2268 host->cmd_status = 0;
2270 dw_mci_request_end(host, mrq);
2275 &host->pending_events))
2283 host->state = state;
2285 spin_unlock(&host->lock);
2290 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2292 memcpy((void *)&host->part_buf, buf, cnt);
2293 host->part_buf_count = cnt;
2297 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2299 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2300 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2301 host->part_buf_count += cnt;
2306 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2308 cnt = min_t(int, cnt, host->part_buf_count);
2310 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2312 host->part_buf_count -= cnt;
2313 host->part_buf_start += cnt;
2319 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2321 memcpy(buf, &host->part_buf, cnt);
2322 host->part_buf_start = cnt;
2323 host->part_buf_count = (1 << host->data_shift) - cnt;
2326 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2328 struct mmc_data *data = host->data;
2332 if (unlikely(host->part_buf_count)) {
2333 int len = dw_mci_push_part_bytes(host, buf, cnt);
2337 if (host->part_buf_count == 2) {
2338 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2339 host->part_buf_count = 0;
2355 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2363 mci_fifo_writew(host->fifo_reg, *pdata++);
2368 dw_mci_set_part_bytes(host, buf, cnt);
2372 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2376 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2388 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2400 *pdata++ = mci_fifo_readw(host->fifo_reg);
2404 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2405 dw_mci_pull_final_bytes(host, buf, cnt);
2409 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2411 struct mmc_data *data = host->data;
2415 if (unlikely(host->part_buf_count)) {
2416 int len = dw_mci_push_part_bytes(host, buf, cnt);
2420 if (host->part_buf_count == 4) {
2421 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2422 host->part_buf_count = 0;
2438 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2446 mci_fifo_writel(host->fifo_reg, *pdata++);
2451 dw_mci_set_part_bytes(host, buf, cnt);
2455 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2459 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2471 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2483 *pdata++ = mci_fifo_readl(host->fifo_reg);
2487 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2488 dw_mci_pull_final_bytes(host, buf, cnt);
2492 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2494 struct mmc_data *data = host->data;
2498 if (unlikely(host->part_buf_count)) {
2499 int len = dw_mci_push_part_bytes(host, buf, cnt);
2504 if (host->part_buf_count == 8) {
2505 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2506 host->part_buf_count = 0;
2522 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2530 mci_fifo_writeq(host->fifo_reg, *pdata++);
2535 dw_mci_set_part_bytes(host, buf, cnt);
2539 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2543 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2555 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2568 *pdata++ = mci_fifo_readq(host->fifo_reg);
2572 host->part_buf = mci_fifo_readq(host->fifo_reg);
2573 dw_mci_pull_final_bytes(host, buf, cnt);
2577 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2582 len = dw_mci_pull_part_bytes(host, buf, cnt);
2589 host->pull_data(host, buf, cnt);
2592 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2594 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2597 struct mmc_data *data = host->data;
2598 int shift = host->data_shift;
2607 host->sg = sg_miter->piter.sg;
2613 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2614 << shift) + host->part_buf_count;
2618 dw_mci_pull_data(host, (void *)(buf + offset), len);
2625 status = mci_readl(host, MINTSTS);
2626 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2629 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2641 host->sg = NULL;
2643 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2646 static void dw_mci_write_data_pio(struct dw_mci *host)
2648 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2651 struct mmc_data *data = host->data;
2652 int shift = host->data_shift;
2655 unsigned int fifo_depth = host->fifo_depth;
2662 host->sg = sg_miter->piter.sg;
2669 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2670 << shift) - host->part_buf_count;
2674 host->push_data(host, (void *)(buf + offset), len);
2681 status = mci_readl(host, MINTSTS);
2682 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2695 host->sg = NULL;
2697 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2700 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2702 del_timer(&host->cto_timer);
2704 if (!host->cmd_status)
2705 host->cmd_status = status;
2709 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2710 tasklet_schedule(&host->tasklet);
2712 dw_mci_start_fault_timer(host);
2715 static void dw_mci_handle_cd(struct dw_mci *host)
2717 struct dw_mci_slot *slot = host->slot;
2720 msecs_to_jiffies(host->pdata->detect_delay_ms));
2725 struct dw_mci *host = dev_id;
2727 struct dw_mci_slot *slot = host->slot;
2729 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2733 if ((host->state == STATE_SENDING_CMD11) &&
2735 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2742 spin_lock(&host->irq_lock);
2743 dw_mci_cmd_interrupt(host, pending);
2744 spin_unlock(&host->irq_lock);
2746 del_timer(&host->cmd11_timer);
2750 spin_lock(&host->irq_lock);
2752 del_timer(&host->cto_timer);
2753 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2754 host->cmd_status = pending;
2756 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2758 spin_unlock(&host->irq_lock);
2762 spin_lock(&host->irq_lock);
2764 if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT)
2765 del_timer(&host->dto_timer);
2768 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2769 host->data_status = pending;
2771 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2773 if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT)
2776 &host->pending_events);
2778 tasklet_schedule(&host->tasklet);
2780 spin_unlock(&host->irq_lock);
2784 spin_lock(&host->irq_lock);
2786 del_timer(&host->dto_timer);
2788 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2789 if (!host->data_status)
2790 host->data_status = pending;
2792 if (host->dir_status == DW_MCI_RECV_STATUS) {
2793 if (host->sg != NULL)
2794 dw_mci_read_data_pio(host, true);
2796 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2797 tasklet_schedule(&host->tasklet);
2799 spin_unlock(&host->irq_lock);
2803 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2804 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2805 dw_mci_read_data_pio(host, false);
2809 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2810 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2811 dw_mci_write_data_pio(host);
2815 spin_lock(&host->irq_lock);
2817 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2818 dw_mci_cmd_interrupt(host, pending);
2820 spin_unlock(&host->irq_lock);
2824 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2825 dw_mci_handle_cd(host);
2829 mci_writel(host, RINTSTS,
2837 if (host->use_dma != TRANS_MODE_IDMAC)
2841 if (host->dma_64bit_address == 1) {
2842 pending = mci_readl(host, IDSTS64);
2844 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2846 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2847 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2848 host->dma_ops->complete((void *)host);
2851 pending = mci_readl(host, IDSTS);
2853 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2855 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2856 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2857 host->dma_ops->complete((void *)host);
2866 struct dw_mci *host = slot->host;
2867 const struct dw_mci_drv_data *drv_data = host->drv_data;
2871 if (host->pdata->caps)
2872 mmc->caps = host->pdata->caps;
2874 if (host->pdata->pm_caps)
2875 mmc->pm_caps = host->pdata->pm_caps;
2880 if (host->dev->of_node) {
2881 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2885 ctrl_id = to_platform_device(host->dev)->id;
2890 dev_err(host->dev, "invalid controller id %d\n",
2897 if (host->pdata->caps2)
2898 mmc->caps2 = host->pdata->caps2;
2900 /* if host has set a minimum_freq, we should respect it */
2901 if (host->minimum_speed)
2902 mmc->f_min = host->minimum_speed;
2916 static int dw_mci_init_slot(struct dw_mci *host)
2922 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2928 slot->sdio_id = host->sdio_id0 + slot->id;
2930 slot->host = host;
2931 host->slot = slot;
2952 if (host->use_dma == TRANS_MODE_IDMAC) {
2953 mmc->max_segs = host->ring_size;
2956 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2958 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2996 slot->host->slot = NULL;
3000 static void dw_mci_init_dma(struct dw_mci *host)
3003 struct device *dev = host->dev;
3016 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
3017 if (host->use_dma == DMA_INTERFACE_IDMA) {
3018 host->use_dma = TRANS_MODE_IDMAC;
3019 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
3020 host->use_dma == DMA_INTERFACE_GDMA) {
3021 host->use_dma = TRANS_MODE_EDMAC;
3027 if (host->use_dma == TRANS_MODE_IDMAC) {
3032 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
3035 /* host supports IDMAC in 64-bit address mode */
3036 host->dma_64bit_address = 1;
3037 dev_info(host->dev,
3039 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
3040 dma_set_coherent_mask(host->dev,
3043 /* host supports IDMAC in 32-bit address mode */
3044 host->dma_64bit_address = 0;
3045 dev_info(host->dev,
3050 host->sg_cpu = dmam_alloc_coherent(host->dev,
3052 &host->sg_dma, GFP_KERNEL);
3053 if (!host->sg_cpu) {
3054 dev_err(host->dev,
3060 host->dma_ops = &dw_mci_idmac_ops;
3061 dev_info(host->dev, "Using internal DMA controller.\n");
3068 host->dma_ops = &dw_mci_edmac_ops;
3069 dev_info(host->dev, "Using external DMA controller.\n");
3072 if (host->dma_ops->init && host->dma_ops->start &&
3073 host->dma_ops->stop && host->dma_ops->cleanup) {
3074 if (host->dma_ops->init(host)) {
3075 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
3080 dev_err(host->dev, "DMA initialization not found.\n");
3087 dev_info(host->dev, "Using PIO mode.\n");
3088 host->use_dma = TRANS_MODE_PIO;
3093 struct dw_mci *host = from_timer(host, t, cmd11_timer);
3095 if (host->state != STATE_SENDING_CMD11) {
3096 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
3100 host->cmd_status = SDMMC_INT_RTO;
3101 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3102 tasklet_schedule(&host->tasklet);
3107 struct dw_mci *host = from_timer(host, t, cto_timer);
3111 spin_lock_irqsave(&host->irq_lock, irqflags);
3121 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3124 dev_warn(host->dev, "Unexpected interrupt latency\n");
3127 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
3129 dev_warn(host->dev, "CTO timeout when already completed\n");
3137 switch (host->state) {
3146 host->cmd_status = SDMMC_INT_RTO;
3147 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3148 tasklet_schedule(&host->tasklet);
3151 dev_warn(host->dev, "Unexpected command timeout, state %d\n",
3152 host->state);
3157 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3162 struct dw_mci *host = from_timer(host, t, dto_timer);
3166 spin_lock_irqsave(&host->irq_lock, irqflags);
3172 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3175 dev_warn(host->dev, "Unexpected data interrupt latency\n");
3178 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) {
3180 dev_warn(host->dev, "DTO timeout when already completed\n");
3188 switch (host->state) {
3196 host->data_status = SDMMC_INT_DRTO;
3197 set_bit(EVENT_DATA_ERROR, &host->pending_events);
3198 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3199 tasklet_schedule(&host->tasklet);
3202 dev_warn(host->dev, "Unexpected data timeout, state %d\n",
3203 host->state);
3208 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3212 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3215 struct device *dev = host->dev;
3216 const struct dw_mci_drv_data *drv_data = host->drv_data;
3236 device_property_read_u32(dev, "data-addr", &host->data_addr_override);
3239 host->wm_aligned = true;
3245 ret = drv_data->parse_dt(host);
3254 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3260 static void dw_mci_enable_cd(struct dw_mci *host)
3269 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3272 if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
3273 spin_lock_irqsave(&host->irq_lock, irqflags);
3274 temp = mci_readl(host, INTMASK);
3276 mci_writel(host, INTMASK, temp);
3277 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3281 int dw_mci_probe(struct dw_mci *host)
3283 const struct dw_mci_drv_data *drv_data = host->drv_data;
3287 if (!host->pdata) {
3288 host->pdata = dw_mci_parse_dt(host);
3289 if (IS_ERR(host->pdata))
3290 return dev_err_probe(host->dev, PTR_ERR(host->pdata),
3294 host->biu_clk = devm_clk_get(host->dev, "biu");
3295 if (IS_ERR(host->biu_clk)) {
3296 dev_dbg(host->dev, "biu clock not available\n");
3298 ret = clk_prepare_enable(host->biu_clk);
3300 dev_err(host->dev, "failed to enable biu clock\n");
3305 host->ciu_clk = devm_clk_get(host->dev, "ciu");
3306 if (IS_ERR(host->ciu_clk)) {
3307 dev_dbg(host->dev, "ciu clock not available\n");
3308 host->bus_hz = host->pdata->bus_hz;
3310 ret = clk_prepare_enable(host->ciu_clk);
3312 dev_err(host->dev, "failed to enable ciu clock\n");
3316 if (host->pdata->bus_hz) {
3317 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3319 dev_warn(host->dev,
3321 host->pdata->bus_hz);
3323 host->bus_hz = clk_get_rate(host->ciu_clk);
3326 if (!host->bus_hz) {
3327 dev_err(host->dev,
3333 if (host->pdata->rstc) {
3334 reset_control_assert(host->pdata->rstc);
3336 reset_control_deassert(host->pdata->rstc);
3340 ret = drv_data->init(host);
3342 dev_err(host->dev,
3348 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0);
3349 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0);
3350 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0);
3352 spin_lock_init(&host->lock);
3353 spin_lock_init(&host->irq_lock);
3354 INIT_LIST_HEAD(&host->queue);
3356 dw_mci_init_fault(host);
3359 * Get the host data width - this assumes that HCON has been set with
3362 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3364 host->push_data = dw_mci_push_data16;
3365 host->pull_data = dw_mci_pull_data16;
3367 host->data_shift = 1;
3369 host->push_data = dw_mci_push_data64;
3370 host->pull_data = dw_mci_pull_data64;
3372 host->data_shift = 3;
3376 "HCON reports a reserved host data width!\n"
3378 host->push_data = dw_mci_push_data32;
3379 host->pull_data = dw_mci_pull_data32;
3381 host->data_shift = 2;
3385 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3390 host->dma_ops = host->pdata->dma_ops;
3391 dw_mci_init_dma(host);
3393 /* Clear the interrupts for the host controller */
3394 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3395 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3398 mci_writel(host, TMOUT, 0xFFFFFFFF);
3404 if (!host->pdata->fifo_depth) {
3411 fifo_size = mci_readl(host, FIFOTH);
3414 fifo_size = host->pdata->fifo_depth;
3416 host->fifo_depth = fifo_size;
3417 host->fifoth_val =
3419 mci_writel(host, FIFOTH, host->fifoth_val);
3422 mci_writel(host, CLKENA, 0);
3423 mci_writel(host, CLKSRC, 0);
3429 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3430 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3432 if (host->data_addr_override)
3433 host->fifo_reg = host->regs + host->data_addr_override;
3434 else if (host->verid < DW_MMC_240A)
3435 host->fifo_reg = host->regs + DATA_OFFSET;
3437 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3439 tasklet_setup(&host->tasklet, dw_mci_tasklet_func);
3440 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3441 host->irq_flags, "dw-mci", host);
3449 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3453 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3455 dev_info(host->dev,
3456 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3457 host->irq, width, fifo_size);
3460 ret = dw_mci_init_slot(host);
3462 dev_dbg(host->dev, "slot %d init failed\n", i);
3467 dw_mci_enable_cd(host);
3472 if (host->use_dma && host->dma_ops->exit)
3473 host->dma_ops->exit(host);
3475 reset_control_assert(host->pdata->rstc);
3478 clk_disable_unprepare(host->ciu_clk);
3481 clk_disable_unprepare(host->biu_clk);
3487 void dw_mci_remove(struct dw_mci *host)
3489 dev_dbg(host->dev, "remove slot\n");
3490 if (host->slot)
3491 dw_mci_cleanup_slot(host->slot);
3493 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3494 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3497 mci_writel(host, CLKENA, 0);
3498 mci_writel(host, CLKSRC, 0);
3500 if (host->use_dma && host->dma_ops->exit)
3501 host->dma_ops->exit(host);
3503 reset_control_assert(host->pdata->rstc);
3505 clk_disable_unprepare(host->ciu_clk);
3506 clk_disable_unprepare(host->biu_clk);
3515 struct dw_mci *host = dev_get_drvdata(dev);
3517 if (host->use_dma && host->dma_ops->exit)
3518 host->dma_ops->exit(host);
3520 clk_disable_unprepare(host->ciu_clk);
3522 if (host->slot &&
3523 (mmc_can_gpio_cd(host->slot->mmc) ||
3524 !mmc_card_is_removable(host->slot->mmc)))
3525 clk_disable_unprepare(host->biu_clk);
3534 struct dw_mci *host = dev_get_drvdata(dev);
3536 if (host->slot &&
3537 (mmc_can_gpio_cd(host->slot->mmc) ||
3538 !mmc_card_is_removable(host->slot->mmc))) {
3539 ret = clk_prepare_enable(host->biu_clk);
3544 ret = clk_prepare_enable(host->ciu_clk);
3548 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3549 clk_disable_unprepare(host->ciu_clk);
3554 if (host->use_dma && host->dma_ops->init)
3555 host->dma_ops->init(host);
3561 mci_writel(host, FIFOTH, host->fifoth_val);
3562 host->prev_blksz = 0;
3565 mci_writel(host, TMOUT, 0xFFFFFFFF);
3567 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3568 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3571 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3574 if (host->slot && host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3575 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
3578 dw_mci_setup_bus(host->slot, true);
3581 if (sdio_irq_claimed(host->slot->mmc))
3582 __dw_mci_enable_sdio_irq(host->slot, 1);
3585 dw_mci_enable_cd(host);
3590 if (host->slot &&
3591 (mmc_can_gpio_cd(host->slot->mmc) ||
3592 !mmc_card_is_removable(host->slot->mmc)))
3593 clk_disable_unprepare(host->biu_clk);