Lines Matching defs:clock
282 * We need to disable low power mode (automatic clock stop)
284 * since stopping the clock is a specific part of the UHS
289 * ever called with a non-zero clock. That shouldn't happen
1207 unsigned int clock = slot->clock;
1218 if (!clock) {
1221 } else if (clock != host->current_speed || force_clkinit) {
1222 div = host->bus_hz / clock;
1223 if (host->bus_hz % clock && host->bus_hz > clock)
1230 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1232 if ((clock != slot->__clk_old &&
1239 slot->id, host->bus_hz, clock,
1248 slot->mmc->f_min == clock)
1252 /* disable clock */
1259 /* set clock to desired speed */
1265 /* enable clock; only low power if no SDIO */
1274 /* keep the last clock value that was requested from core */
1275 slot->__clk_old = clock;
1280 host->current_speed = clock;
1344 /* this is the first command, send the initialization clock */
1475 * Use mirror of ios->clock to prevent race with mmc
1478 slot->clock = ios->clock;
1520 /* Adjust clock / bus width after power is up */
1525 /* Turn clock off before power goes down */
1543 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1653 * Low power mode will stop the card clock when idle. According to the
1785 /* if the controller reset bit did clear, then set clock regs */
1788 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1801 /* After a CTRL reset we need to have CIU set clock registers */
3241 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
3296 dev_dbg(host->dev, "biu clock not available\n");
3300 dev_err(host->dev, "failed to enable biu clock\n");
3307 dev_dbg(host->dev, "ciu clock not available\n");
3312 dev_err(host->dev, "failed to enable ciu clock\n");
3421 /* disable clock to CIU */
3496 /* disable clock to CIU */
3577 /* Force setup bus to guarantee available clock output */