Lines Matching refs:phase
70 * Set the drive phase offset based on speed mode to achieve hold times.
96 int phase;
99 * In almost all cases a 90 degree phase offset will provide
104 phase = 90;
110 * bus width is 8 we need to double the phase offset
114 phase = 180;
126 phase = 180;
130 clk_set_phase(priv->drv_clk, phase);
165 /* Try each phase and extract good ranges */
215 dev_info(host->dev, "All phases work, using default phase %d.",
232 dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
241 dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
251 dev_info(host->dev, "Successfully tuned phase to %d\n",
276 if (of_property_read_u32(np, "rockchip,default-sample-phase",