Lines Matching refs:base
173 void __iomem *base;
247 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR);
251 iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3));
256 *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR);
260 ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3));
342 writel(0x1FFF, host->base + DAVINCI_MMCTOR);
365 writel(cmd->arg, host->base + DAVINCI_MMCARGHL);
366 writel(cmd_reg, host->base + DAVINCI_MMCCMD);
380 writel(im_val, host->base + DAVINCI_MMCIM);
527 writel(0, host->base + DAVINCI_MMCBLEN);
528 writel(0, host->base + DAVINCI_MMCNBLK);
542 writel(timeout, host->base + DAVINCI_MMCTOD);
543 writel(data->blocks, host->base + DAVINCI_MMCNBLK);
544 writel(data->blksz, host->base + DAVINCI_MMCBLEN);
550 host->base + DAVINCI_MMCFIFOCTL);
552 host->base + DAVINCI_MMCFIFOCTL);
556 host->base + DAVINCI_MMCFIFOCTL);
558 host->base + DAVINCI_MMCFIFOCTL);
594 mmcst1 = readl(host->base + DAVINCI_MMCST1);
657 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
659 writel(temp, host->base + DAVINCI_MMCCLK);
670 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN;
671 writel(temp, host->base + DAVINCI_MMCCLK);
675 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
677 writel(temp, host->base + DAVINCI_MMCCLK);
679 writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
710 writel((readl(host->base + DAVINCI_MMCCTL) &
712 host->base + DAVINCI_MMCCTL);
717 writel((readl(host->base + DAVINCI_MMCCTL) &
719 host->base + DAVINCI_MMCCTL);
721 writel(readl(host->base + DAVINCI_MMCCTL) |
723 host->base + DAVINCI_MMCCTL);
728 writel(readl(host->base + DAVINCI_MMCCTL) &
730 host->base + DAVINCI_MMCCTL);
732 writel(readl(host->base + DAVINCI_MMCCTL) &
734 host->base + DAVINCI_MMCCTL);
746 writel(0, host->base + DAVINCI_MMCARGHL);
747 writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD);
749 u32 tmp = readl(host->base + DAVINCI_MMCST0);
775 if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) &
777 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
793 writel(0, host->base + DAVINCI_MMCIM);
807 cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01);
808 cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23);
809 cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45);
810 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
813 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
821 writel(0, host->base + DAVINCI_MMCIM);
831 temp = readl(host->base + DAVINCI_MMCCTL);
837 writel(temp, host->base + DAVINCI_MMCCTL);
853 status = readl(host->base + DAVINCI_SDIOIST);
857 writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
872 status = readl(host->base + DAVINCI_MMCST0);
876 writel(0, host->base + DAVINCI_MMCIM);
880 status = readl(host->base + DAVINCI_MMCST0);
900 im_val = readl(host->base + DAVINCI_MMCIM);
901 writel(0, host->base + DAVINCI_MMCIM);
905 status = readl(host->base + DAVINCI_MMCST0);
916 writel(im_val, host->base + DAVINCI_MMCIM);
960 u32 temp = readb(host->base + DAVINCI_MMCDRSP);
1035 if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) {
1036 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
1040 writel(readl(host->base + DAVINCI_SDIOIEN) |
1041 SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN);
1045 writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN,
1046 host->base + DAVINCI_SDIOIEN);
1111 writel(0, host->base + DAVINCI_MMCCLK);
1112 writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
1114 writel(0x1FFF, host->base + DAVINCI_MMCTOR);
1115 writel(0xFFFF, host->base + DAVINCI_MMCTOD);
1219 host->base = devm_ioremap(&pdev->dev, mem->start, mem_size);
1220 if (!host->base) {
1363 writel(0, host->base + DAVINCI_MMCIM);