Lines Matching defs:DAVINCI_MMCCLK
33 #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */
77 /* DAVINCI_MMCCLK definitions */
657 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
659 writel(temp, host->base + DAVINCI_MMCCLK);
670 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN;
671 writel(temp, host->base + DAVINCI_MMCCLK);
675 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
677 writel(temp, host->base + DAVINCI_MMCCLK);
679 writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
1111 writel(0, host->base + DAVINCI_MMCCLK);
1112 writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);