Lines Matching defs:clock
55 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
153 int clock; /* Current clock speed */
266 host->clock = 0;
1092 static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
1103 * clock. CMD15 must be used to return to data mode, so this
1106 * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
1112 * BUT, the 3-bit clock divisor in data mode is too small if
1113 * the core clock is higher than 250MHz, so instead use the
1115 * clock divisor at all times.
1118 if (clock < 100000) {
1119 /* Can't stop the clock, but make it as slow as possible
1127 div = host->max_clk / clock;
1130 if ((host->max_clk / div) > clock)
1137 clock = host->max_clk / (div + 2);
1138 mmc->actual_clock = clock;
1142 host->ns_per_fifo_word = (1000000000 / clock) *
1231 if (!ios->clock || ios->clock != host->clock) {
1232 bcm2835_set_clock(host, ios->clock);
1233 host->clock = ios->clock;
1243 /* Disable clever clock switching, to cope with fast core clocks */