Lines Matching defs:blade
266 nid = uv_blade_to_memory_nid(bid);/* -1 if no memory on blade */
317 * We target the cores of a blade and not the hyperthreads themselves.
318 * There is a max of 8 cores per socket and 2 sockets per blade,
357 irq_handler_t irq_handler, int cpu, int blade)
388 static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
407 irq_handler_t irq_handler, int cpu, int blade)
417 irq = uv_setup_irq(irq_name, cpu, blade, mmr, UV_AFFINITY_CPU);
431 gru_base[blade]->bs_grus[chiplet].gs_irq[core] = irq;
435 static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
442 irq = gru_base[blade]->bs_grus[chiplet].gs_irq[core];
454 int blade;
458 blade = uv_cpu_to_blade_id(cpu);
459 gru_chiplet_teardown_tlb_irq(0, cpu, blade);
460 gru_chiplet_teardown_tlb_irq(1, cpu, blade);
462 for_each_possible_blade(blade) {
463 if (uv_blade_nr_possible_cpus(blade))
465 gru_chiplet_teardown_tlb_irq(0, 0, blade);
466 gru_chiplet_teardown_tlb_irq(1, 0, blade);
472 int blade;
477 blade = uv_cpu_to_blade_id(cpu);
478 ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru0_intr, cpu, blade);
482 ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru1_intr, cpu, blade);
486 for_each_possible_blade(blade) {
487 if (uv_blade_nr_possible_cpus(blade))
489 ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru_intr_mblade, 0, blade);
493 ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru_intr_mblade, 0, blade);