Lines Matching refs:val

8 #define EXTRACT_BIT(val, bit) (!!(val & BIT(bit)))
9 #define EXTRACT_BITS(val, s, e) ((val & GENMASK(e, s)) >> s)
79 u16 val;
92 pci_read_config_word(dev, pos + PCI_PASID_CAP, &val);
93 fn->max_pasid_log = EXTRACT_BITS(val, 8, 12);
120 u32 val;
129 pci_read_config_dword(dev, pos + OCXL_DVSEC_FUNC_OFF_INDEX, &val);
130 afu_present = EXTRACT_BIT(val, 31);
136 fn->max_afu_index = EXTRACT_BITS(val, 24, 29);
230 int ocxl_config_get_reset_reload(struct pci_dev *dev, int *val)
242 *val = !!(reset_reload & BIT(0));
246 int ocxl_config_set_reset_reload(struct pci_dev *dev, int val)
257 if (val)
327 u32 val;
338 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
339 while (!EXTRACT_BIT(val, 31)) {
347 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
426 u32 val, *ptr;
430 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_NAME + i, &val);
434 *ptr = le32_to_cpu((__force __le32) val);
444 u32 val;
449 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL, &val);
452 afu->global_mmio_bar = EXTRACT_BITS(val, 0, 2);
453 afu->global_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
455 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL + 4, &val);
458 afu->global_mmio_offset += (u64) val << 32;
460 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ, &val);
463 afu->global_mmio_size = val;
468 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP, &val);
471 afu->pp_mmio_bar = EXTRACT_BITS(val, 0, 2);
472 afu->pp_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
474 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP + 4, &val);
477 afu->pp_mmio_offset += (u64) val << 32;
479 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP_SZ, &val);
482 afu->pp_mmio_stride = val;
742 u16 val;
744 val = actag_count & OCXL_DVSEC_ACTAG_MASK;
745 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_EN, val);
747 val = actag_base & OCXL_DVSEC_ACTAG_MASK;
748 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_BASE, val);
777 u8 val;
779 pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, &val);
781 val |= 1;
783 val &= 0xFE;
784 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, val);
790 u32 val;
835 val = recv_cap >> 32;
836 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP, val);
837 val = recv_cap & GENMASK(31, 0);
838 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP + 4, val);
846 &val);
848 *be32ptr = cpu_to_be32(val);
850 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP, &val);
851 recv_cap = (long) val << 32;
852 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP + 4, &val);
853 recv_cap |= val;
889 u32 val;
893 &val);
894 if (EXTRACT_BIT(val, 20)) {
901 val &= ~OCXL_DVSEC_PASID_MASK;
902 val |= pasid & OCXL_DVSEC_PASID_MASK;
903 val |= BIT(20);
906 val);
910 &val);
911 while (EXTRACT_BIT(val, 20)) {
921 &val);
930 u32 val;
932 val = (tag_first & OCXL_DVSEC_ACTAG_MASK) << 16;
933 val |= tag_count & OCXL_DVSEC_ACTAG_MASK;
935 val);