Lines Matching refs:dev
34 static int find_dvsec(struct pci_dev *dev, int dvsec_id)
36 return pci_find_dvsec_capability(dev, PCI_VENDOR_ID_IBM, dvsec_id);
39 static int find_dvsec_afu_ctrl(struct pci_dev *dev, u8 afu_idx)
45 while ((vsec = pci_find_next_ext_capability(dev, vsec,
47 pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
49 pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
53 pci_read_config_byte(dev,
65 * @dev: PCI device to match
69 static struct pci_dev *get_function_0(struct pci_dev *dev)
71 unsigned int devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
73 return pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus),
74 dev->bus->number, devfn);
77 static void read_pasid(struct pci_dev *dev, struct ocxl_fn_config *fn)
82 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PASID);
88 dev_dbg(&dev->dev, "Function doesn't require any PASID\n");
92 pci_read_config_word(dev, pos + PCI_PASID_CAP, &val);
96 dev_dbg(&dev->dev, "PASID capability:\n");
97 dev_dbg(&dev->dev, " Max PASID log = %d\n", fn->max_pasid_log);
100 static int read_dvsec_tl(struct pci_dev *dev, struct ocxl_fn_config *fn)
104 pos = find_dvsec(dev, OCXL_DVSEC_TL_ID);
105 if (!pos && PCI_FUNC(dev->devfn) == 0) {
106 dev_err(&dev->dev, "Can't find TL DVSEC\n");
109 if (pos && PCI_FUNC(dev->devfn) != 0) {
110 dev_err(&dev->dev, "TL DVSEC is only allowed on function 0\n");
117 static int read_dvsec_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
122 pos = find_dvsec(dev, OCXL_DVSEC_FUNC_ID);
124 dev_err(&dev->dev, "Can't find function DVSEC\n");
129 pci_read_config_dword(dev, pos + OCXL_DVSEC_FUNC_OFF_INDEX, &val);
133 dev_dbg(&dev->dev, "Function doesn't define any AFU\n");
139 dev_dbg(&dev->dev, "Function DVSEC:\n");
140 dev_dbg(&dev->dev, " Max AFU index = %d\n", fn->max_afu_index);
144 static int read_dvsec_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn)
153 pos = find_dvsec(dev, OCXL_DVSEC_AFU_INFO_ID);
155 dev_err(&dev->dev, "Can't find AFU information DVSEC\n");
162 static int read_dvsec_vendor(struct pci_dev *dev)
175 if (PCI_FUNC(dev->devfn) != 0)
178 pos = find_dvsec(dev, OCXL_DVSEC_VENDOR_ID);
182 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_CFG_VERS, &cfg);
183 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_TLX_VERS, &tlx);
184 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_DLX_VERS, &dlx);
185 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
188 dev_dbg(&dev->dev, "Vendor specific DVSEC:\n");
189 dev_dbg(&dev->dev, " CFG version = 0x%x\n", cfg);
190 dev_dbg(&dev->dev, " TLX version = 0x%x\n", tlx);
191 dev_dbg(&dev->dev, " DLX version = 0x%x\n", dlx);
192 dev_dbg(&dev->dev, " ResetReload = 0x%x\n", reset_reload);
198 * @dev: PCI device to match
208 static int get_dvsec_vendor0(struct pci_dev *dev, struct pci_dev **dev0,
213 if (PCI_FUNC(dev->devfn) != 0) {
214 dev = get_function_0(dev);
215 if (!dev)
218 dev = pci_dev_get(dev);
220 pos = find_dvsec(dev, OCXL_DVSEC_VENDOR_ID);
222 pci_dev_put(dev);
225 *dev0 = dev;
230 int ocxl_config_get_reset_reload(struct pci_dev *dev, int *val)
236 if (get_dvsec_vendor0(dev, &dev0, &pos))
246 int ocxl_config_set_reset_reload(struct pci_dev *dev, int val)
252 if (get_dvsec_vendor0(dev, &dev0, &pos))
267 static int validate_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
270 dev_err(&dev->dev,
276 dev_err(&dev->dev,
284 int ocxl_config_read_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
288 read_pasid(dev, fn);
290 rc = read_dvsec_tl(dev, fn);
292 dev_err(&dev->dev,
298 rc = read_dvsec_function(dev, fn);
300 dev_err(&dev->dev,
305 rc = read_dvsec_afu_info(dev, fn);
307 dev_err(&dev->dev, "Invalid AFU configuration: %d\n", rc);
311 rc = read_dvsec_vendor(dev);
313 dev_err(&dev->dev,
319 rc = validate_function(dev, fn);
324 static int read_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn,
333 dev_err(&dev->dev, "Invalid offset in AFU info DVSEC\n");
337 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, offset);
338 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
341 dev_err(&dev->dev,
347 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
349 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_DATA, data);
355 * @dev: the device for the AFU
362 static int read_template_version(struct pci_dev *dev, struct ocxl_fn_config *fn,
369 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_VERSION, &val32);
380 int ocxl_config_check_afu_index(struct pci_dev *dev,
387 pci_write_config_byte(dev,
391 rc = read_template_version(dev, fn, &len, &templ_version);
399 dev_dbg(&dev->dev, "AFU descriptor template version %d.%d\n",
411 dev_warn(&dev->dev, "Unknown AFU template version %#x\n",
416 dev_warn(&dev->dev,
422 static int read_afu_name(struct pci_dev *dev, struct ocxl_fn_config *fn,
430 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_NAME + i, &val);
440 static int read_afu_mmio(struct pci_dev *dev, struct ocxl_fn_config *fn,
449 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL, &val);
455 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL + 4, &val);
460 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ, &val);
468 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP, &val);
474 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP + 4, &val);
479 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP_SZ, &val);
487 static int read_afu_control(struct pci_dev *dev, struct ocxl_afu_config *afu)
493 pos = find_dvsec_afu_ctrl(dev, afu->idx);
495 dev_err(&dev->dev, "Can't find AFU control DVSEC for AFU %d\n",
501 pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_SUP, &val8);
504 pci_read_config_word(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_SUP, &val16);
525 static int validate_afu(struct pci_dev *dev, struct ocxl_afu_config *afu)
530 dev_err(&dev->dev, "Empty AFU name\n");
535 dev_err(&dev->dev,
544 dev_err(&dev->dev, "Invalid global MMIO bar number\n");
550 dev_err(&dev->dev, "Invalid per-process MMIO bar number\n");
558 * @dev: the device for the AFU
564 static int read_afu_lpc_memory_info(struct pci_dev *dev,
590 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_ALL_MEM_SZ, &val32);
610 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_LPC_MEM_START, &val32);
616 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_LPC_MEM_START + 4, &val32);
622 rc = read_template_version(dev, fn, &templ_len, &templ_version);
627 rc = read_afu_info(dev, fn,
633 rc = read_afu_info(dev, fn,
652 int ocxl_config_read_afu(struct pci_dev *dev, struct ocxl_fn_config *fn,
664 pci_write_config_byte(dev,
668 rc = read_afu_name(dev, fn, afu);
672 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_AFU_VERSION, &val32);
681 rc = read_afu_mmio(dev, fn, afu);
685 rc = read_afu_lpc_memory_info(dev, fn, afu);
689 rc = read_afu_control(dev, afu);
693 dev_dbg(&dev->dev, "AFU configuration:\n");
694 dev_dbg(&dev->dev, " name = %s\n", afu->name);
695 dev_dbg(&dev->dev, " version = %d.%d\n", afu->version_major,
697 dev_dbg(&dev->dev, " global mmio bar = %hhu\n", afu->global_mmio_bar);
698 dev_dbg(&dev->dev, " global mmio offset = %#llx\n",
700 dev_dbg(&dev->dev, " global mmio size = %#x\n", afu->global_mmio_size);
701 dev_dbg(&dev->dev, " pp mmio bar = %hhu\n", afu->pp_mmio_bar);
702 dev_dbg(&dev->dev, " pp mmio offset = %#llx\n", afu->pp_mmio_offset);
703 dev_dbg(&dev->dev, " pp mmio stride = %#x\n", afu->pp_mmio_stride);
704 dev_dbg(&dev->dev, " lpc_mem offset = %#llx\n", afu->lpc_mem_offset);
705 dev_dbg(&dev->dev, " lpc_mem size = %#llx\n", afu->lpc_mem_size);
706 dev_dbg(&dev->dev, " special purpose mem offset = %#llx\n",
708 dev_dbg(&dev->dev, " special purpose mem size = %#llx\n",
710 dev_dbg(&dev->dev, " pasid supported (log) = %u\n",
712 dev_dbg(&dev->dev, " actag supported = %u\n",
715 rc = validate_afu(dev, afu);
720 int ocxl_config_get_actag_info(struct pci_dev *dev, u16 *base, u16 *enabled,
730 rc = pnv_ocxl_get_actag(dev, base, enabled, supported);
732 dev_err(&dev->dev, "Can't get actag for device: %d\n", rc);
739 void ocxl_config_set_afu_actag(struct pci_dev *dev, int pos, int actag_base,
745 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_EN, val);
748 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_BASE, val);
752 int ocxl_config_get_pasid_info(struct pci_dev *dev, int *count)
754 return pnv_ocxl_get_pasid_count(dev, count);
757 void ocxl_config_set_afu_pasid(struct pci_dev *dev, int pos, int pasid_base,
764 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_EN, val8);
766 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
770 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
775 void ocxl_config_set_afu_state(struct pci_dev *dev, int pos, int enable)
779 pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, &val);
784 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, val);
788 int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec)
800 if (PCI_FUNC(dev->devfn) != 0)
824 rc = pnv_ocxl_get_tl_cap(dev, &recv_cap, recv_rate,
831 pci_write_config_dword(dev,
836 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP, val);
838 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP + 4, val);
844 pci_read_config_dword(dev,
850 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP, &val);
852 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP + 4, &val);
855 rc = pnv_ocxl_set_tl_conf(dev, recv_cap, __pa(recv_rate),
877 pci_write_config_byte(dev, tl_dvsec + OCXL_DVSEC_TL_BACKOFF_TIMERS,
887 int ocxl_config_terminate_pasid(struct pci_dev *dev, int afu_control, int pasid)
892 pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
895 dev_err(&dev->dev,
904 pci_write_config_dword(dev,
909 pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
913 dev_err(&dev->dev,
919 pci_read_config_dword(dev,
927 void ocxl_config_set_actag(struct pci_dev *dev, int func_dvsec, u32 tag_first,
934 pci_write_config_dword(dev, func_dvsec + OCXL_DVSEC_FUNC_OFF_ACTAG,