Lines Matching refs:dev
55 * @dev: the device structure
59 static inline u32 mei_me_mecbrw_read(const struct mei_device *dev)
61 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
67 * @dev: the device structure
70 static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data)
72 mei_me_reg_write(to_me_hw(dev), H_CB_WW, data);
78 * @dev: the device structure
82 static inline u32 mei_me_mecsr_read(const struct mei_device *dev)
86 reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA);
87 trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg);
95 * @dev: the device structure
99 static inline u32 mei_hcsr_read(const struct mei_device *dev)
103 reg = mei_me_reg_read(to_me_hw(dev), H_CSR);
104 trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg);
112 * @dev: the device structure
115 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg)
117 trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg);
118 mei_me_reg_write(to_me_hw(dev), H_CSR, reg);
125 * @dev: the device structure
128 static inline void mei_hcsr_set(struct mei_device *dev, u32 reg)
131 mei_hcsr_write(dev, reg);
137 * @dev: the device structure
139 static inline void mei_hcsr_set_hig(struct mei_device *dev)
143 hcsr = mei_hcsr_read(dev) | H_IG;
144 mei_hcsr_set(dev, hcsr);
150 * @dev: the device structure
154 static inline u32 mei_me_d0i3c_read(const struct mei_device *dev)
158 reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C);
159 trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg);
167 * @dev: the device structure
170 static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg)
172 trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg);
173 mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg);
179 * @dev: mei device
184 static int mei_me_trc_status(struct mei_device *dev, u32 *trc)
186 struct mei_me_hw *hw = to_me_hw(dev);
192 trace_mei_reg_read(dev->dev, "ME_TRC", ME_TRC, *trc);
200 * @dev: mei device
205 static int mei_me_fw_status(struct mei_device *dev,
208 struct mei_me_hw *hw = to_me_hw(dev);
218 ret = hw->read_fws(dev, fw_src->status[i],
220 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_X",
233 * @dev: mei device
240 static int mei_me_hw_config(struct mei_device *dev)
242 struct mei_me_hw *hw = to_me_hw(dev);
249 hcsr = mei_hcsr_read(dev);
253 hw->read_fws(dev, PCI_CFG_HFS_1, ®);
254 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
260 reg = mei_me_d0i3c_read(dev);
272 * @dev: mei device
276 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
278 struct mei_me_hw *hw = to_me_hw(dev);
292 * @dev: the device structure
295 static inline void me_intr_disable(struct mei_device *dev, u32 hcsr)
298 mei_hcsr_set(dev, hcsr);
304 * @dev: the device structure
307 static inline void me_intr_clear(struct mei_device *dev, u32 hcsr)
310 mei_hcsr_write(dev, hcsr);
316 * @dev: the device structure
318 static void mei_me_intr_clear(struct mei_device *dev)
320 u32 hcsr = mei_hcsr_read(dev);
322 me_intr_clear(dev, hcsr);
327 * @dev: the device structure
329 static void mei_me_intr_enable(struct mei_device *dev)
333 if (mei_me_hw_use_polling(to_me_hw(dev)))
336 hcsr = mei_hcsr_read(dev) | H_CSR_IE_MASK;
337 mei_hcsr_set(dev, hcsr);
343 * @dev: the device structure
345 static void mei_me_intr_disable(struct mei_device *dev)
347 u32 hcsr = mei_hcsr_read(dev);
349 me_intr_disable(dev, hcsr);
355 * @dev: the device structure
357 static void mei_me_synchronize_irq(struct mei_device *dev)
359 struct mei_me_hw *hw = to_me_hw(dev);
370 * @dev: the device structure
372 static void mei_me_hw_reset_release(struct mei_device *dev)
374 u32 hcsr = mei_hcsr_read(dev);
378 mei_hcsr_set(dev, hcsr);
384 * @dev: mei device
386 static void mei_me_host_set_ready(struct mei_device *dev)
388 u32 hcsr = mei_hcsr_read(dev);
390 if (!mei_me_hw_use_polling(to_me_hw(dev)))
394 mei_hcsr_set(dev, hcsr);
400 * @dev: mei device
403 static bool mei_me_host_is_ready(struct mei_device *dev)
405 u32 hcsr = mei_hcsr_read(dev);
413 * @dev: mei device
416 static bool mei_me_hw_is_ready(struct mei_device *dev)
418 u32 mecsr = mei_me_mecsr_read(dev);
426 * @dev: mei device
429 static bool mei_me_hw_is_resetting(struct mei_device *dev)
431 u32 mecsr = mei_me_mecsr_read(dev);
439 * @dev: the device structure
441 static void mei_gsc_pxp_check(struct mei_device *dev)
443 struct mei_me_hw *hw = to_me_hw(dev);
446 if (dev->pxp_mode == MEI_DEV_PXP_DEFAULT)
449 hw->read_fws(dev, PCI_CFG_HFS_5, &fwsts5);
450 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_5", PCI_CFG_HFS_5, fwsts5);
452 dev_dbg(dev->dev, "pxp mode is ready 0x%08x\n", fwsts5);
453 dev->pxp_mode = MEI_DEV_PXP_READY;
455 dev_dbg(dev->dev, "pxp mode is not ready 0x%08x\n", fwsts5);
463 * @dev: mei device
466 static int mei_me_hw_ready_wait(struct mei_device *dev)
468 mutex_unlock(&dev->device_lock);
469 wait_event_timeout(dev->wait_hw_ready,
470 dev->recvd_hw_ready,
471 dev->timeouts.hw_ready);
472 mutex_lock(&dev->device_lock);
473 if (!dev->recvd_hw_ready) {
474 dev_err(dev->dev, "wait hw ready failed\n");
478 mei_gsc_pxp_check(dev);
480 mei_me_hw_reset_release(dev);
481 dev->recvd_hw_ready = false;
488 * @dev: mei device
491 static int mei_me_hw_start(struct mei_device *dev)
493 int ret = mei_me_hw_ready_wait(dev);
497 dev_dbg(dev->dev, "hw is ready\n");
499 mei_me_host_set_ready(dev);
507 * @dev: the device structure
511 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
516 hcsr = mei_hcsr_read(dev);
527 * @dev: the device structure
531 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
533 return mei_hbuf_filled_slots(dev) == 0;
539 * @dev: the device structure
543 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
545 struct mei_me_hw *hw = to_me_hw(dev);
548 filled_slots = mei_hbuf_filled_slots(dev);
561 * @dev: the device structure
565 static u32 mei_me_hbuf_depth(const struct mei_device *dev)
567 struct mei_me_hw *hw = to_me_hw(dev);
575 * @dev: the device structure
583 static int mei_me_hbuf_write(struct mei_device *dev,
597 dev_err(dev->dev, "wrong parameters null data with data_len = %zu\n", data_len);
601 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr));
603 empty_slots = mei_hbuf_empty_slots(dev);
604 dev_dbg(dev->dev, "empty slots = %d.\n", empty_slots);
615 mei_me_hcbww_write(dev, reg_buf[i]);
619 mei_me_hcbww_write(dev, reg_buf[i]);
626 mei_me_hcbww_write(dev, reg);
629 mei_hcsr_set_hig(dev);
630 if (!mei_me_hw_is_ready(dev))
639 * @dev: the device structure
643 static int mei_me_count_full_read_slots(struct mei_device *dev)
649 me_csr = mei_me_mecsr_read(dev);
659 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots);
666 * @dev: the device structure
672 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
678 *reg_buf++ = mei_me_mecbrw_read(dev);
681 u32 reg = mei_me_mecbrw_read(dev);
686 mei_hcsr_set_hig(dev);
693 * @dev: the device structure
695 static void mei_me_pg_set(struct mei_device *dev)
697 struct mei_me_hw *hw = to_me_hw(dev);
701 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
705 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
712 * @dev: the device structure
714 static void mei_me_pg_unset(struct mei_device *dev)
716 struct mei_me_hw *hw = to_me_hw(dev);
720 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
726 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
733 * @dev: the device structure
737 static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
739 struct mei_me_hw *hw = to_me_hw(dev);
742 dev->pg_event = MEI_PG_EVENT_WAIT;
744 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
748 mutex_unlock(&dev->device_lock);
749 wait_event_timeout(dev->wait_pg,
750 dev->pg_event == MEI_PG_EVENT_RECEIVED,
751 dev->timeouts.pgi);
752 mutex_lock(&dev->device_lock);
754 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
755 mei_me_pg_set(dev);
761 dev->pg_event = MEI_PG_EVENT_IDLE;
770 * @dev: the device structure
774 static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
776 struct mei_me_hw *hw = to_me_hw(dev);
779 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
782 dev->pg_event = MEI_PG_EVENT_WAIT;
784 mei_me_pg_unset(dev);
786 mutex_unlock(&dev->device_lock);
787 wait_event_timeout(dev->wait_pg,
788 dev->pg_event == MEI_PG_EVENT_RECEIVED,
789 dev->timeouts.pgi);
790 mutex_lock(&dev->device_lock);
793 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
798 dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
799 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);
803 mutex_unlock(&dev->device_lock);
804 wait_event_timeout(dev->wait_pg,
805 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
806 dev->timeouts.pgi);
807 mutex_lock(&dev->device_lock);
809 if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED)
815 dev->pg_event = MEI_PG_EVENT_IDLE;
824 * @dev: the device structure
828 static bool mei_me_pg_in_transition(struct mei_device *dev)
830 return dev->pg_event >= MEI_PG_EVENT_WAIT &&
831 dev->pg_event <= MEI_PG_EVENT_INTR_WAIT;
837 * @dev: the device structure
841 static bool mei_me_pg_is_enabled(struct mei_device *dev)
843 struct mei_me_hw *hw = to_me_hw(dev);
844 u32 reg = mei_me_mecsr_read(dev);
852 if (!dev->hbm_f_pg_supported)
858 dev_dbg(dev->dev, "pg: not supported: d0i3 = %d HGP = %d hbm version %d.%d ?= %d.%d\n",
861 dev->version.major_version,
862 dev->version.minor_version,
872 * @dev: the device structure
877 static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr)
879 u32 reg = mei_me_d0i3c_read(dev);
886 mei_me_d0i3c_write(dev, reg);
888 reg = mei_me_d0i3c_read(dev);
895 * @dev: the device structure
899 static u32 mei_me_d0i3_unset(struct mei_device *dev)
901 u32 reg = mei_me_d0i3c_read(dev);
905 mei_me_d0i3c_write(dev, reg);
907 reg = mei_me_d0i3c_read(dev);
914 * @dev: the device structure
918 static int mei_me_d0i3_enter_sync(struct mei_device *dev)
920 struct mei_me_hw *hw = to_me_hw(dev);
924 reg = mei_me_d0i3c_read(dev);
927 dev_dbg(dev->dev, "d0i3 set not needed\n");
933 dev->pg_event = MEI_PG_EVENT_WAIT;
935 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
940 mutex_unlock(&dev->device_lock);
941 wait_event_timeout(dev->wait_pg,
942 dev->pg_event == MEI_PG_EVENT_RECEIVED,
943 dev->timeouts.pgi);
944 mutex_lock(&dev->device_lock);
946 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
952 dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
954 reg = mei_me_d0i3_set(dev, true);
956 dev_dbg(dev->dev, "d0i3 enter wait not needed\n");
961 mutex_unlock(&dev->device_lock);
962 wait_event_timeout(dev->wait_pg,
963 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
964 dev->timeouts.d0i3);
965 mutex_lock(&dev->device_lock);
967 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
968 reg = mei_me_d0i3c_read(dev);
979 dev->pg_event = MEI_PG_EVENT_IDLE;
980 dev_dbg(dev->dev, "d0i3 enter ret = %d\n", ret);
990 * @dev: the device structure
994 static int mei_me_d0i3_enter(struct mei_device *dev)
996 struct mei_me_hw *hw = to_me_hw(dev);
999 reg = mei_me_d0i3c_read(dev);
1002 dev_dbg(dev->dev, "already d0i3 : set not needed\n");
1006 mei_me_d0i3_set(dev, false);
1009 dev->pg_event = MEI_PG_EVENT_IDLE;
1010 dev_dbg(dev->dev, "d0i3 enter\n");
1017 * @dev: the device structure
1021 static int mei_me_d0i3_exit_sync(struct mei_device *dev)
1023 struct mei_me_hw *hw = to_me_hw(dev);
1027 dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
1029 reg = mei_me_d0i3c_read(dev);
1032 dev_dbg(dev->dev, "d0i3 exit not needed\n");
1037 reg = mei_me_d0i3_unset(dev);
1039 dev_dbg(dev->dev, "d0i3 exit wait not needed\n");
1044 mutex_unlock(&dev->device_lock);
1045 wait_event_timeout(dev->wait_pg,
1046 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
1047 dev->timeouts.d0i3);
1048 mutex_lock(&dev->device_lock);
1050 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
1051 reg = mei_me_d0i3c_read(dev);
1062 dev->pg_event = MEI_PG_EVENT_IDLE;
1064 dev_dbg(dev->dev, "d0i3 exit ret = %d\n", ret);
1072 * @dev: the device structure
1074 static void mei_me_pg_legacy_intr(struct mei_device *dev)
1076 struct mei_me_hw *hw = to_me_hw(dev);
1078 if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT)
1081 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;
1083 if (waitqueue_active(&dev->wait_pg))
1084 wake_up(&dev->wait_pg);
1090 * @dev: the device structure
1093 static void mei_me_d0i3_intr(struct mei_device *dev, u32 intr_source)
1095 struct mei_me_hw *hw = to_me_hw(dev);
1097 if (dev->pg_event == MEI_PG_EVENT_INTR_WAIT &&
1099 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;
1102 if (dev->hbm_state != MEI_HBM_IDLE) {
1107 dev_dbg(dev->dev, "d0i3 set host ready\n");
1108 mei_me_host_set_ready(dev);
1114 wake_up(&dev->wait_pg);
1123 dev_dbg(dev->dev, "d0i3 want resume\n");
1124 mei_hbm_pg_resume(dev);
1131 * @dev: the device structure
1134 static void mei_me_pg_intr(struct mei_device *dev, u32 intr_source)
1136 struct mei_me_hw *hw = to_me_hw(dev);
1139 mei_me_d0i3_intr(dev, intr_source);
1141 mei_me_pg_legacy_intr(dev);
1147 * @dev: the device structure
1151 int mei_me_pg_enter_sync(struct mei_device *dev)
1153 struct mei_me_hw *hw = to_me_hw(dev);
1156 return mei_me_d0i3_enter_sync(dev);
1158 return mei_me_pg_legacy_enter_sync(dev);
1164 * @dev: the device structure
1168 int mei_me_pg_exit_sync(struct mei_device *dev)
1170 struct mei_me_hw *hw = to_me_hw(dev);
1173 return mei_me_d0i3_exit_sync(dev);
1175 return mei_me_pg_legacy_exit_sync(dev);
1181 * @dev: the device structure
1186 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
1188 struct mei_me_hw *hw = to_me_hw(dev);
1193 mei_me_intr_enable(dev);
1195 ret = mei_me_d0i3_exit_sync(dev);
1203 pm_runtime_set_active(dev->dev);
1205 hcsr = mei_hcsr_read(dev);
1212 dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);
1214 mei_hcsr_set(dev, hcsr);
1215 hcsr = mei_hcsr_read(dev);
1220 if (!intr_enable || mei_me_hw_use_polling(to_me_hw(dev)))
1223 dev->recvd_hw_ready = false;
1224 mei_hcsr_write(dev, hcsr);
1230 hcsr = mei_hcsr_read(dev);
1233 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);
1236 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);
1239 mei_me_hw_reset_release(dev);
1241 ret = mei_me_d0i3_enter(dev);
1259 struct mei_device *dev = (struct mei_device *)dev_id;
1262 hcsr = mei_hcsr_read(dev);
1266 dev_dbg(dev->dev, "interrupt source 0x%08X\n", me_intr_src(hcsr));
1269 me_intr_disable(dev, hcsr);
1286 struct mei_device *dev = (struct mei_device *) dev_id;
1292 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n");
1294 mutex_lock(&dev->device_lock);
1296 hcsr = mei_hcsr_read(dev);
1297 me_intr_clear(dev, hcsr);
1302 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
1303 dev_warn(dev->dev, "FW not ready: resetting: dev_state = %d pxp = %d\n",
1304 dev->dev_state, dev->pxp_mode);
1305 if (dev->dev_state == MEI_DEV_POWERING_DOWN ||
1306 dev->dev_state == MEI_DEV_POWER_DOWN)
1307 mei_cl_all_disconnect(dev);
1308 else if (dev->dev_state != MEI_DEV_DISABLED)
1309 schedule_work(&dev->reset_work);
1313 if (mei_me_hw_is_resetting(dev))
1314 mei_hcsr_set_hig(dev);
1316 mei_me_pg_intr(dev, me_intr_src(hcsr));
1318 /* check if we need to start the dev */
1319 if (!mei_host_is_ready(dev)) {
1320 if (mei_hw_is_ready(dev)) {
1321 dev_dbg(dev->dev, "we need to start the dev.\n");
1322 dev->recvd_hw_ready = true;
1323 wake_up(&dev->wait_hw_ready);
1325 dev_dbg(dev->dev, "Spurious Interrupt\n");
1330 slots = mei_count_full_read_slots(dev);
1332 dev_dbg(dev->dev, "slots to read = %08x\n", slots);
1333 rets = mei_irq_read_handler(dev, &cmpl_list, &slots);
1342 dev_err(dev->dev, "mei_irq_read_handler ret = %d, state = %d.\n",
1343 rets, dev->dev_state);
1344 if (dev->dev_state != MEI_DEV_RESETTING &&
1345 dev->dev_state != MEI_DEV_DISABLED &&
1346 dev->dev_state != MEI_DEV_POWERING_DOWN &&
1347 dev->dev_state != MEI_DEV_POWER_DOWN)
1348 schedule_work(&dev->reset_work);
1353 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1360 if (dev->pg_event != MEI_PG_EVENT_WAIT &&
1361 dev->pg_event != MEI_PG_EVENT_RECEIVED) {
1362 rets = mei_irq_write_handler(dev, &cmpl_list);
1363 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1366 mei_irq_compl_handler(dev, &cmpl_list);
1369 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
1370 mei_me_intr_enable(dev);
1371 mutex_unlock(&dev->device_lock);
1397 struct mei_device *dev = _dev;
1401 dev_dbg(dev->dev, "kernel thread is running\n");
1403 struct mei_me_hw *hw = to_me_hw(dev);
1413 hcsr = mei_hcsr_read(dev);
1416 irq_ret = mei_me_irq_thread_handler(1, dev);
1418 dev_err(dev->dev, "irq_ret %d\n", irq_ret);
1486 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg);
1512 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
1537 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_3", PCI_CFG_HFS_3, reg);
1540 dev_dbg(&pdev->dev, "fw type is %d\n", fw_type);
1748 struct mei_device *dev;
1752 dev = devm_kzalloc(parent, sizeof(*dev) + sizeof(*hw), GFP_KERNEL);
1753 if (!dev)
1756 hw = to_me_hw(dev);
1759 dev->dr_dscr[i].size = cfg->dma_size[i];
1761 mei_device_init(dev, parent, slow_fw, &mei_me_hw_ops);
1764 dev->fw_f_fw_ver_supported = cfg->fw_ver_supported;
1766 dev->kind = cfg->kind;
1768 return dev;