Lines Matching refs:edev
68 static inline bool has_quirk_single_word_read(struct eeprom_93xx46_dev *edev)
70 return edev->pdata->quirks & EEPROM_93XX46_QUIRK_SINGLE_WORD_READ;
73 static inline bool has_quirk_instruction_length(struct eeprom_93xx46_dev *edev)
75 return edev->pdata->quirks & EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH;
78 static inline bool has_quirk_extra_read_cycle(struct eeprom_93xx46_dev *edev)
80 return edev->pdata->quirks & EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE;
86 struct eeprom_93xx46_dev *edev = priv;
91 if (unlikely(off >= edev->size))
93 if ((off + count) > edev->size)
94 count = edev->size - off;
98 mutex_lock(&edev->lock);
100 if (edev->pdata->prepare)
101 edev->pdata->prepare(edev);
104 bits = edev->addrlen + 3;
109 u16 cmd_addr = OP_READ << edev->addrlen;
112 if (edev->pdata->flags & EE_ADDR8) {
114 if (has_quirk_single_word_read(edev))
118 if (has_quirk_single_word_read(edev))
122 dev_dbg(&edev->spi->dev, "read cmd 0x%x, %d Hz\n",
123 cmd_addr, edev->spi->max_speed_hz);
125 if (has_quirk_extra_read_cycle(edev)) {
142 err = spi_sync(edev->spi, &m);
147 dev_err(&edev->spi->dev, "read %zu bytes at %d: err. %d\n",
157 if (edev->pdata->finish)
158 edev->pdata->finish(edev);
160 mutex_unlock(&edev->lock);
165 static int eeprom_93xx46_ew(struct eeprom_93xx46_dev *edev, int is_on)
173 bits = edev->addrlen + 3;
175 cmd_addr = OP_START << edev->addrlen;
176 if (edev->pdata->flags & EE_ADDR8)
181 if (has_quirk_instruction_length(edev)) {
186 dev_dbg(&edev->spi->dev, "ew%s cmd 0x%04x, %d bits\n",
197 mutex_lock(&edev->lock);
199 if (edev->pdata->prepare)
200 edev->pdata->prepare(edev);
202 ret = spi_sync(edev->spi, &m);
206 dev_err(&edev->spi->dev, "erase/write %sable error %d\n",
209 if (edev->pdata->finish)
210 edev->pdata->finish(edev);
212 mutex_unlock(&edev->lock);
217 eeprom_93xx46_write_word(struct eeprom_93xx46_dev *edev,
225 if (unlikely(off >= edev->size))
229 bits = edev->addrlen + 3;
231 cmd_addr = OP_WRITE << edev->addrlen;
233 if (edev->pdata->flags & EE_ADDR8) {
241 dev_dbg(&edev->spi->dev, "write cmd 0x%x\n", cmd_addr);
256 ret = spi_sync(edev->spi, &m);
265 struct eeprom_93xx46_dev *edev = priv;
269 if (unlikely(off >= edev->size))
271 if ((off + count) > edev->size)
272 count = edev->size - off;
277 if (edev->pdata->flags & EE_ADDR16) {
283 ret = eeprom_93xx46_ew(edev, 1);
287 mutex_lock(&edev->lock);
289 if (edev->pdata->prepare)
290 edev->pdata->prepare(edev);
293 ret = eeprom_93xx46_write_word(edev, &buf[i], off + i);
295 dev_err(&edev->spi->dev, "write failed at %d: %d\n",
301 if (edev->pdata->finish)
302 edev->pdata->finish(edev);
304 mutex_unlock(&edev->lock);
307 eeprom_93xx46_ew(edev, 0);
311 static int eeprom_93xx46_eral(struct eeprom_93xx46_dev *edev)
313 struct eeprom_93xx46_platform_data *pd = edev->pdata;
320 bits = edev->addrlen + 3;
322 cmd_addr = OP_START << edev->addrlen;
323 if (edev->pdata->flags & EE_ADDR8)
328 if (has_quirk_instruction_length(edev)) {
333 dev_dbg(&edev->spi->dev, "eral cmd 0x%04x, %d bits\n", cmd_addr, bits);
343 mutex_lock(&edev->lock);
345 if (edev->pdata->prepare)
346 edev->pdata->prepare(edev);
348 ret = spi_sync(edev->spi, &m);
350 dev_err(&edev->spi->dev, "erase error %d\n", ret);
355 pd->finish(edev);
357 mutex_unlock(&edev->lock);
365 struct eeprom_93xx46_dev *edev = dev_get_drvdata(dev);
370 ret = eeprom_93xx46_ew(edev, 1);
373 ret = eeprom_93xx46_eral(edev);
376 ret = eeprom_93xx46_ew(edev, 0);
386 struct eeprom_93xx46_dev *edev = context;
388 gpiod_set_value_cansleep(edev->pdata->select, 1);
393 struct eeprom_93xx46_dev *edev = context;
395 gpiod_set_value_cansleep(edev->pdata->select, 0);
481 struct eeprom_93xx46_dev *edev;
496 edev = devm_kzalloc(&spi->dev, sizeof(*edev), GFP_KERNEL);
497 if (!edev)
501 edev->size = 128;
503 edev->size = 256;
505 edev->size = 512;
512 edev->addrlen = ilog2(edev->size);
514 edev->addrlen = ilog2(edev->size) - 1;
520 mutex_init(&edev->lock);
522 edev->spi = spi;
523 edev->pdata = pd;
525 edev->nvmem_config.type = NVMEM_TYPE_EEPROM;
526 edev->nvmem_config.name = dev_name(&spi->dev);
527 edev->nvmem_config.dev = &spi->dev;
528 edev->nvmem_config.read_only = pd->flags & EE_READONLY;
529 edev->nvmem_config.root_only = true;
530 edev->nvmem_config.owner = THIS_MODULE;
531 edev->nvmem_config.compat = true;
532 edev->nvmem_config.base_dev = &spi->dev;
533 edev->nvmem_config.reg_read = eeprom_93xx46_read;
534 edev->nvmem_config.reg_write = eeprom_93xx46_write;
535 edev->nvmem_config.priv = edev;
536 edev->nvmem_config.stride = 4;
537 edev->nvmem_config.word_size = 1;
538 edev->nvmem_config.size = edev->size;
540 edev->nvmem = devm_nvmem_register(&spi->dev, &edev->nvmem_config);
541 if (IS_ERR(edev->nvmem))
542 return PTR_ERR(edev->nvmem);
546 edev->size,
554 spi_set_drvdata(spi, edev);
560 struct eeprom_93xx46_dev *edev = spi_get_drvdata(spi);
562 if (!(edev->pdata->flags & EE_READONLY))