Lines Matching refs:vsec
29 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \
31 pci_read_config_word(dev, vsec + 0x6, dest); \
34 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
35 pci_read_config_byte(dev, vsec + 0x8, dest)
37 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
38 pci_read_config_byte(dev, vsec + 0x9, dest)
50 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
51 pci_read_config_byte(dev, vsec + 0xa, dest)
52 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
53 pci_write_config_byte(dev, vsec + 0xa, val)
60 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
61 pci_read_config_word(dev, vsec + 0xc, dest)
62 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
63 pci_read_config_byte(dev, vsec + 0xe, dest)
64 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
65 pci_read_config_byte(dev, vsec + 0xf, dest)
66 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
67 pci_read_config_word(dev, vsec + 0x10, dest)
69 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
70 pci_read_config_byte(dev, vsec + 0x13, dest)
71 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
72 pci_write_config_byte(dev, vsec + 0x13, val)
77 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
78 pci_read_config_dword(dev, vsec + 0x20, dest)
79 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
80 pci_read_config_dword(dev, vsec + 0x24, dest)
81 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
82 pci_read_config_dword(dev, vsec + 0x28, dest)
83 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
84 pci_read_config_dword(dev, vsec + 0x2c, dest)
158 int vsec;
183 if (!(vsec = find_cxl_vsec(dev)))
187 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
189 pci_read_config_dword(dev, vsec + 0x0, &val);
193 pci_read_config_dword(dev, vsec + 0x4, &val);
197 pci_read_config_dword(dev, vsec + 0x8, &val);
202 pci_read_config_dword(dev, vsec + 0xc, &val);
205 pci_read_config_dword(dev, vsec + 0x10, &val);
212 pci_read_config_dword(dev, vsec + 0x14, &val);
214 pci_read_config_dword(dev, vsec + 0x18, &val);
216 pci_read_config_dword(dev, vsec + 0x1c, &val);
219 pci_read_config_dword(dev, vsec + 0x20, &val);
221 pci_read_config_dword(dev, vsec + 0x24, &val);
223 pci_read_config_dword(dev, vsec + 0x28, &val);
225 pci_read_config_dword(dev, vsec + 0x2c, &val);
228 pci_read_config_dword(dev, vsec + 0x30, &val);
230 pci_read_config_dword(dev, vsec + 0x34, &val);
232 pci_read_config_dword(dev, vsec + 0x38, &val);
234 pci_read_config_dword(dev, vsec + 0x3c, &val);
237 pci_read_config_dword(dev, vsec + 0x40, &val);
239 pci_read_config_dword(dev, vsec + 0x44, &val);
242 pci_read_config_dword(dev, vsec + 0x48, &val);
244 pci_read_config_dword(dev, vsec + 0x4c, &val);
247 pci_read_config_dword(dev, vsec + 0x50, &val);
249 pci_read_config_dword(dev, vsec + 0x54, &val);
251 pci_read_config_dword(dev, vsec + 0x58, &val);
253 pci_read_config_dword(dev, vsec + 0x58, &val);
659 int vsec;
662 if (!(vsec = find_cxl_vsec(dev))) {
667 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
682 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
743 int vsec;
749 if (!(vsec = find_cxl_vsec(dev))) {
754 if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) {
760 if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) {
1283 int vsec;
1289 if (!(vsec = find_cxl_vsec(dev))) {
1294 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
1300 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
1301 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
1302 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
1303 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
1304 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
1305 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
1310 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
1311 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
1312 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
1313 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
1314 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);