Lines Matching refs:val
52 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
53 pci_write_config_byte(dev, vsec + 0xa, val)
71 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
72 pci_write_config_byte(dev, vsec + 0x13, val)
91 #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit)))
92 #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
95 #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15)
96 #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31)
97 #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47)
98 #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48)
99 #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
100 #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59)
101 #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61)
102 #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63)
104 #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
107 #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6)
108 #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7)
109 #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
112 #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
159 u32 val;
163 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
164 dev_info(&dev->dev, "BAR0: %#.8x\n", val);
165 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
166 dev_info(&dev->dev, "BAR1: %#.8x\n", val);
167 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
168 dev_info(&dev->dev, "BAR2: %#.8x\n", val);
169 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
170 dev_info(&dev->dev, "BAR3: %#.8x\n", val);
171 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
172 dev_info(&dev->dev, "BAR4: %#.8x\n", val);
173 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
174 dev_info(&dev->dev, "BAR5: %#.8x\n", val);
189 pci_read_config_dword(dev, vsec + 0x0, &val);
190 show_reg("Cap ID", (val >> 0) & 0xffff);
191 show_reg("Cap Ver", (val >> 16) & 0xf);
192 show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
193 pci_read_config_dword(dev, vsec + 0x4, &val);
194 show_reg("VSEC ID", (val >> 0) & 0xffff);
195 show_reg("VSEC Rev", (val >> 16) & 0xf);
196 show_reg("VSEC Length", (val >> 20) & 0xfff);
197 pci_read_config_dword(dev, vsec + 0x8, &val);
198 show_reg("Num AFUs", (val >> 0) & 0xff);
199 show_reg("Status", (val >> 8) & 0xff);
200 show_reg("Mode Control", (val >> 16) & 0xff);
201 show_reg("Reserved", (val >> 24) & 0xff);
202 pci_read_config_dword(dev, vsec + 0xc, &val);
203 show_reg("PSL Rev", (val >> 0) & 0xffff);
204 show_reg("CAIA Ver", (val >> 16) & 0xffff);
205 pci_read_config_dword(dev, vsec + 0x10, &val);
206 show_reg("Base Image Rev", (val >> 0) & 0xffff);
207 show_reg("Reserved", (val >> 16) & 0x0fff);
208 show_reg("Image Control", (val >> 28) & 0x3);
209 show_reg("Reserved", (val >> 30) & 0x1);
210 show_reg("Image Loaded", (val >> 31) & 0x1);
212 pci_read_config_dword(dev, vsec + 0x14, &val);
213 show_reg("Reserved", val);
214 pci_read_config_dword(dev, vsec + 0x18, &val);
215 show_reg("Reserved", val);
216 pci_read_config_dword(dev, vsec + 0x1c, &val);
217 show_reg("Reserved", val);
219 pci_read_config_dword(dev, vsec + 0x20, &val);
220 show_reg("AFU Descriptor Offset", val);
221 pci_read_config_dword(dev, vsec + 0x24, &val);
222 show_reg("AFU Descriptor Size", val);
223 pci_read_config_dword(dev, vsec + 0x28, &val);
224 show_reg("Problem State Offset", val);
225 pci_read_config_dword(dev, vsec + 0x2c, &val);
226 show_reg("Problem State Size", val);
228 pci_read_config_dword(dev, vsec + 0x30, &val);
229 show_reg("Reserved", val);
230 pci_read_config_dword(dev, vsec + 0x34, &val);
231 show_reg("Reserved", val);
232 pci_read_config_dword(dev, vsec + 0x38, &val);
233 show_reg("Reserved", val);
234 pci_read_config_dword(dev, vsec + 0x3c, &val);
235 show_reg("Reserved", val);
237 pci_read_config_dword(dev, vsec + 0x40, &val);
238 show_reg("PSL Programming Port", val);
239 pci_read_config_dword(dev, vsec + 0x44, &val);
240 show_reg("PSL Programming Control", val);
242 pci_read_config_dword(dev, vsec + 0x48, &val);
243 show_reg("Reserved", val);
244 pci_read_config_dword(dev, vsec + 0x4c, &val);
245 show_reg("Reserved", val);
247 pci_read_config_dword(dev, vsec + 0x50, &val);
248 show_reg("Flash Address Register", val);
249 pci_read_config_dword(dev, vsec + 0x54, &val);
250 show_reg("Flash Size Register", val);
251 pci_read_config_dword(dev, vsec + 0x58, &val);
252 show_reg("Flash Status/Control Register", val);
253 pci_read_config_dword(dev, vsec + 0x58, &val);
254 show_reg("Flash Data Port", val);
261 u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
267 val = AFUD_READ_INFO(afu);
268 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
269 show_reg("num_of_processes", AFUD_NUM_PROCS(val));
270 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
271 show_reg("req_prog_mode", val & 0xffffULL);
272 afu_cr_num = AFUD_NUM_CRS(val);
274 val = AFUD_READ(afu, 0x8);
275 show_reg("Reserved", val);
276 val = AFUD_READ(afu, 0x10);
277 show_reg("Reserved", val);
278 val = AFUD_READ(afu, 0x18);
279 show_reg("Reserved", val);
281 val = AFUD_READ_CR(afu);
282 show_reg("Reserved", (val >> (63-7)) & 0xff);
283 show_reg("AFU_CR_len", AFUD_CR_LEN(val));
284 afu_cr_len = AFUD_CR_LEN(val) * 256;
286 val = AFUD_READ_CR_OFF(afu);
287 afu_cr_off = val;
288 show_reg("AFU_CR_offset", val);
290 val = AFUD_READ_PPPSA(afu);
291 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
292 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
294 val = AFUD_READ_PPPSA_OFF(afu);
295 show_reg("PerProcessPSA_offset", val);
297 val = AFUD_READ_EB(afu);
298 show_reg("Reserved", (val >> (63-7)) & 0xff);
299 show_reg("AFU_EB_len", AFUD_EB_LEN(val));
301 val = AFUD_READ_EB_OFF(afu);
302 show_reg("AFU_EB_offset", val);
305 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
306 show_reg("CR Vendor", val & 0xffff);
307 show_reg("CR Device", (val >> 16) & 0xffff);
744 u8 val;
754 if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) {
758 val &= ~CXL_VSEC_PROTOCOL_MASK;
759 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
760 if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) {
836 u64 val;
838 val = AFUD_READ_INFO(afu);
839 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
840 afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
841 afu->crs_num = AFUD_NUM_CRS(val);
843 if (AFUD_AFU_DIRECTED(val))
845 if (AFUD_DEDICATED_PROCESS(val))
847 if (AFUD_TIME_SLICED(val))
850 val = AFUD_READ_PPPSA(afu);
851 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
852 afu->psa = AFUD_PPPSA_PSA(val);
853 if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
856 val = AFUD_READ_CR(afu);
857 afu->crs_len = AFUD_CR_LEN(val) * 256;
882 u32 val;
894 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
895 if (rc || val == 0) {