Lines Matching refs:ctx
404 static void slb_invalid(struct cxl_context *ctx)
406 struct cxl *adapter = ctx->afu->adapter;
409 WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex));
412 ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) |
413 be32_to_cpu(ctx->elem->lpid));
426 static int do_process_element_cmd(struct cxl_context *ctx,
433 trace_cxl_llcmd(ctx, cmd);
435 WARN_ON(!ctx->afu->enabled);
437 ctx->elem->software_state = cpu_to_be32(pe_state);
439 *(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe);
441 cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe);
444 dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n");
448 if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) {
449 dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n");
453 state = be64_to_cpup(ctx->afu->native->sw_command_status);
460 (cmd | (cmd >> 16) | ctx->pe))
473 trace_cxl_llcmd_done(ctx, cmd, rc);
477 static int add_process_element(struct cxl_context *ctx)
481 mutex_lock(&ctx->afu->native->spa_mutex);
482 pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe);
483 if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V)))
484 ctx->pe_inserted = true;
485 pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe);
486 mutex_unlock(&ctx->afu->native->spa_mutex);
490 static int terminate_process_element(struct cxl_context *ctx)
495 if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V)))
498 mutex_lock(&ctx->afu->native->spa_mutex);
499 pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe);
504 if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
505 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE,
507 ctx->elem->software_state = 0; /* Remove Valid bit */
508 pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe);
509 mutex_unlock(&ctx->afu->native->spa_mutex);
513 static int remove_process_element(struct cxl_context *ctx)
517 mutex_lock(&ctx->afu->native->spa_mutex);
518 pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe);
523 if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
524 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0);
527 ctx->pe_inserted = false;
529 slb_invalid(ctx);
530 pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe);
531 mutex_unlock(&ctx->afu->native->spa_mutex);
536 void cxl_assign_psn_space(struct cxl_context *ctx)
538 if (!ctx->afu->pp_size || ctx->master) {
539 ctx->psn_phys = ctx->afu->psn_phys;
540 ctx->psn_size = ctx->afu->adapter->ps_size;
542 ctx->psn_phys = ctx->afu->psn_phys +
543 (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe);
544 ctx->psn_size = ctx->afu->pp_size;
623 static u64 calculate_sr(struct cxl_context *ctx)
625 return cxl_calculate_sr(ctx->master, ctx->kernel, false,
629 static void update_ivtes_directed(struct cxl_context *ctx)
631 bool need_update = (ctx->status == STARTED);
635 WARN_ON(terminate_process_element(ctx));
636 WARN_ON(remove_process_element(ctx));
640 ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
641 ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
655 WARN_ON(add_process_element(ctx));
658 static int process_element_entry_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
663 cxl_assign_psn_space(ctx);
665 ctx->elem->ctxtime = 0; /* disable */
666 ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
667 ctx->elem->haurp = 0; /* disable */
669 if (ctx->kernel)
672 if (ctx->mm == NULL) {
674 __func__, ctx->pe, pid_nr(ctx->pid));
677 pid = ctx->mm->context.id;
681 if (!(ctx->tidr) && (ctx->assign_tidr)) {
685 ctx->tidr = current->thread.tidr;
686 pr_devel("%s: current tidr: %d\n", __func__, ctx->tidr);
689 ctx->elem->common.tid = cpu_to_be32(ctx->tidr);
690 ctx->elem->common.pid = cpu_to_be32(pid);
692 ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
694 ctx->elem->common.csrp = 0; /* disable */
696 cxl_prefault(ctx, wed);
702 if (ctx->irqs.range[0] == 0) {
703 ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
704 ctx->irqs.range[0] = 1;
707 ctx->elem->common.amr = cpu_to_be64(amr);
708 ctx->elem->common.wed = cpu_to_be64(wed);
713 int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
718 result = process_element_entry_psl9(ctx, wed, amr);
722 update_ivtes_directed(ctx);
725 result = cxl_ops->afu_check_and_enable(ctx->afu);
729 return add_process_element(ctx);
732 int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr)
737 cxl_assign_psn_space(ctx);
739 ctx->elem->ctxtime = 0; /* disable */
740 ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
741 ctx->elem->haurp = 0; /* disable */
742 ctx->elem->u.sdr = cpu_to_be64(mfspr(SPRN_SDR1));
745 if (ctx->kernel)
747 ctx->elem->common.tid = 0;
748 ctx->elem->common.pid = cpu_to_be32(pid);
750 ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
752 ctx->elem->common.csrp = 0; /* disable */
753 ctx->elem->common.u.psl8.aurp0 = 0; /* disable */
754 ctx->elem->common.u.psl8.aurp1 = 0; /* disable */
756 cxl_prefault(ctx, wed);
758 ctx->elem->common.u.psl8.sstp0 = cpu_to_be64(ctx->sstp0);
759 ctx->elem->common.u.psl8.sstp1 = cpu_to_be64(ctx->sstp1);
765 if (ctx->irqs.range[0] == 0) {
766 ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
767 ctx->irqs.range[0] = 1;
770 update_ivtes_directed(ctx);
772 ctx->elem->common.amr = cpu_to_be64(amr);
773 ctx->elem->common.wed = cpu_to_be64(wed);
776 if ((result = cxl_ops->afu_check_and_enable(ctx->afu)))
779 return add_process_element(ctx);
874 void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx)
879 ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
880 ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
884 void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx)
886 struct cxl_afu *afu = ctx->afu;
889 (((u64)ctx->irqs.offset[0] & 0xffff) << 48) |
890 (((u64)ctx->irqs.offset[1] & 0xffff) << 32) |
891 (((u64)ctx->irqs.offset[2] & 0xffff) << 16) |
892 ((u64)ctx->irqs.offset[3] & 0xffff));
894 (((u64)ctx->irqs.range[0] & 0xffff) << 48) |
895 (((u64)ctx->irqs.range[1] & 0xffff) << 32) |
896 (((u64)ctx->irqs.range[2] & 0xffff) << 16) |
897 ((u64)ctx->irqs.range[3] & 0xffff));
900 int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
902 struct cxl_afu *afu = ctx->afu;
906 result = process_element_entry_psl9(ctx, wed, amr);
910 if (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes)
911 afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
913 ctx->elem->software_state = cpu_to_be32(CXL_PE_SOFTWARE_STATE_V);
928 int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr)
930 struct cxl_afu *afu = ctx->afu;
935 if (ctx->kernel)
939 cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx));
941 if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1)))
944 cxl_prefault(ctx, wed);
946 if (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes)
947 afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
952 cxl_assign_psn_space(ctx);
1004 static int native_attach_process(struct cxl_context *ctx, bool kernel,
1007 if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) {
1012 ctx->kernel = kernel;
1013 if ((ctx->afu->current_mode == CXL_MODE_DIRECTED) &&
1014 (ctx->afu->adapter->native->sl_ops->attach_afu_directed))
1015 return ctx->afu->adapter->native->sl_ops->attach_afu_directed(ctx, wed, amr);
1017 if ((ctx->afu->current_mode == CXL_MODE_DEDICATED) &&
1018 (ctx->afu->adapter->native->sl_ops->attach_dedicated_process))
1019 return ctx->afu->adapter->native->sl_ops->attach_dedicated_process(ctx, wed, amr);
1024 static inline int detach_process_native_dedicated(struct cxl_context *ctx)
1042 cxl_ops->afu_reset(ctx->afu);
1043 cxl_afu_disable(ctx->afu);
1044 cxl_psl_purge(ctx->afu);
1048 static void native_update_ivtes(struct cxl_context *ctx)
1050 if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
1051 return update_ivtes_directed(ctx);
1052 if ((ctx->afu->current_mode == CXL_MODE_DEDICATED) &&
1053 (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes))
1054 return ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
1058 static inline int detach_process_native_afu_directed(struct cxl_context *ctx)
1060 if (!ctx->pe_inserted)
1062 if (terminate_process_element(ctx))
1064 if (remove_process_element(ctx))
1070 static int native_detach_process(struct cxl_context *ctx)
1072 trace_cxl_detach(ctx);
1074 if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
1075 return detach_process_native_dedicated(ctx);
1077 return detach_process_native_afu_directed(ctx);
1099 void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx)
1103 fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL9_FIR1);
1105 dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
1106 if (ctx->afu->adapter->native->sl_ops->register_serr_irq) {
1107 serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
1108 cxl_afu_decode_psl_serr(ctx->afu, serr);
1112 void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx)
1116 fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1);
1117 fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2);
1118 fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An);
1119 afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An);
1121 dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
1122 dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2);
1123 if (ctx->afu->adapter->native->sl_ops->register_serr_irq) {
1124 serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
1125 cxl_afu_decode_psl_serr(ctx->afu, serr);
1127 dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
1128 dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
1131 static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx,
1135 dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat);
1137 if (ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers)
1138 ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers(ctx);
1140 if (ctx->afu->adapter->native->sl_ops->debugfs_stop_trace) {
1141 dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n");
1142 ctx->afu->adapter->native->sl_ops->debugfs_stop_trace(ctx->afu->adapter);
1145 return cxl_ops->ack_irq(ctx, 0, errstat);
1172 struct cxl_context *ctx;
1194 ctx = idr_find(&afu->contexts_idr, ph);
1195 if (ctx) {
1197 ret = afu->adapter->native->sl_ops->handle_interrupt(irq, ctx, &irq_info);
1212 static void native_irq_wait(struct cxl_context *ctx)
1223 ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff;
1224 if (ph != ctx->pe)
1226 dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An);
1240 dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i"
1447 static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask)
1449 trace_cxl_psl_irq_ack(ctx, tfc);
1451 cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc);
1453 recover_psl_err(ctx->afu, psl_reset_mask);