Lines Matching refs:ull
199 #define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */
201 #define CXL_PSL_SR_An_XLAT_hpt (0ull << (63-6))/* Hashed page table (HPT) mode */
202 #define CXL_PSL_SR_An_XLAT_roh (2ull << (63-6))/* Radix on HPT mode */
203 #define CXL_PSL_SR_An_XLAT_ror (3ull << (63-6))/* Radix on Radix mode */
204 #define CXL_PSL_SR_An_BOT (1ull << (63-10)) /* Use the in-memory segment table */
206 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
207 #define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */
208 #define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */
209 #define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */
211 #define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */
212 #define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */
215 #define CXL_PSL_ID_An_F (1ull << (63-31))
216 #define CXL_PSL_ID_An_L (1ull << (63-30))
219 #define CXL_PSL_SERR_An_afuto (1ull << (63-0))
220 #define CXL_PSL_SERR_An_afudis (1ull << (63-1))
221 #define CXL_PSL_SERR_An_afuov (1ull << (63-2))
222 #define CXL_PSL_SERR_An_badsrc (1ull << (63-3))
223 #define CXL_PSL_SERR_An_badctx (1ull << (63-4))
224 #define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
225 #define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
226 #define CXL_PSL_SERR_An_afupar (1ull << (63-7))
227 #define CXL_PSL_SERR_An_afudup (1ull << (63-8))
232 #define CXL_PSL_SERR_An_afuto_mask (1ull << (63-32))
233 #define CXL_PSL_SERR_An_afudis_mask (1ull << (63-33))
234 #define CXL_PSL_SERR_An_afuov_mask (1ull << (63-34))
235 #define CXL_PSL_SERR_An_badsrc_mask (1ull << (63-35))
236 #define CXL_PSL_SERR_An_badctx_mask (1ull << (63-36))
237 #define CXL_PSL_SERR_An_llcmdis_mask (1ull << (63-37))
238 #define CXL_PSL_SERR_An_llcmdto_mask (1ull << (63-38))
239 #define CXL_PSL_SERR_An_afupar_mask (1ull << (63-39))
240 #define CXL_PSL_SERR_An_afudup_mask (1ull << (63-40))
246 #define CXL_PSL_SERR_An_AE (1ull << (63-30))
286 #define CXL_SSTP0_An_KS (1ull << (63-2))
287 #define CXL_SSTP0_An_KP (1ull << (63-3))
288 #define CXL_SSTP0_An_N (1ull << (63-4))
289 #define CXL_SSTP0_An_L (1ull << (63-5))
290 #define CXL_SSTP0_An_C (1ull << (63-6))
291 #define CXL_SSTP0_An_TA (1ull << (63-7))
296 (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
297 #define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1)
298 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
299 #define CXL_SSTP1_An_V (1ull << (63-63))
312 #define CXL_TLB_SLB_P (1ull) /* Pending (read) */
315 #define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */
316 #define CXL_TLB_SLB_IQ_LPID (1ull) /* Inv qualifier */
317 #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
320 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
323 #define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */
324 #define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */
325 #define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */
326 #define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */
328 #define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
329 #define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
330 #define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
335 #define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
340 #define CXL_PSL9_DSISR_An_TF (1ull << (63-3)) /* Translation fault */
341 #define CXL_PSL9_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
342 #define CXL_PSL9_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
343 #define CXL_PSL9_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
344 #define CXL_PSL9_DSISR_An_S (1ull << (63-38)) /* TF for a write operation */
360 #define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */
361 #define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */
362 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
363 #define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */
366 #define CXL_PSL_DEBUG_CDC (1ull << (63-27)) /* Coherent Data cache support */
369 #define CXL_XSL9_IERAT_MLPID (1ull << (63-0)) /* Match LPID */
370 #define CXL_XSL9_IERAT_MPID (1ull << (63-1)) /* Match PID */
371 #define CXL_XSL9_IERAT_PRS (1ull << (63-4)) /* PRS bit for Radix invalidations */
372 #define CXL_XSL9_IERAT_INVR (1ull << (63-3)) /* Invalidate Radix */
373 #define CXL_XSL9_IERAT_IALL (1ull << (63-8)) /* Invalidate All */
374 #define CXL_XSL9_IERAT_IINPROG (1ull << (63-63)) /* Invalidate in progress */