Lines Matching refs:pcr
62 static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
64 rtsx_pci_write_register(pcr, MSGTXDATA0,
66 rtsx_pci_write_register(pcr, MSGTXDATA1,
68 rtsx_pci_write_register(pcr, MSGTXDATA2,
70 rtsx_pci_write_register(pcr, MSGTXDATA3,
72 rtsx_pci_write_register(pcr, LTR_CTL, LTR_TX_EN_MASK |
78 int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
80 return rtsx_comm_set_ltr_latency(pcr, latency);
83 static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable)
85 if (pcr->aspm_enabled == enable)
88 if (pcr->aspm_mode == ASPM_MODE_CFG) {
89 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
91 enable ? pcr->aspm_en : 0);
92 } else if (pcr->aspm_mode == ASPM_MODE_REG) {
93 if (pcr->aspm_en & 0x02)
94 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 |
97 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 |
101 if (!enable && (pcr->aspm_en & 0x02))
104 pcr->aspm_enabled = enable;
107 static void rtsx_disable_aspm(struct rtsx_pcr *pcr)
109 if (pcr->ops->set_aspm)
110 pcr->ops->set_aspm(pcr, false);
112 rtsx_comm_set_aspm(pcr, false);
115 int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val)
117 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val);
122 static void rtsx_set_l1off_sub_cfg_d0(struct rtsx_pcr *pcr, int active)
124 if (pcr->ops->set_l1off_cfg_sub_d0)
125 pcr->ops->set_l1off_cfg_sub_d0(pcr, active);
128 static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr)
130 struct rtsx_cr_option *option = &pcr->option;
132 rtsx_disable_aspm(pcr);
138 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
140 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
141 rtsx_set_l1off_sub_cfg_d0(pcr, 1);
144 static void rtsx_pm_full_on(struct rtsx_pcr *pcr)
146 rtsx_comm_pm_full_on(pcr);
149 void rtsx_pci_start_run(struct rtsx_pcr *pcr)
152 if (pcr->remove_pci)
155 if (pcr->state != PDEV_STAT_RUN) {
156 pcr->state = PDEV_STAT_RUN;
157 if (pcr->ops->enable_auto_blink)
158 pcr->ops->enable_auto_blink(pcr);
159 rtsx_pm_full_on(pcr);
164 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
173 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
176 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
188 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
194 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
197 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
212 int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
217 rtsx_pci_write_register(pcr, PHYDATA0, 0xFF, (u8)val);
218 rtsx_pci_write_register(pcr, PHYDATA1, 0xFF, (u8)(val >> 8));
219 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
220 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x81);
223 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
239 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
241 if (pcr->ops->write_phy)
242 return pcr->ops->write_phy(pcr, addr, val);
244 return __rtsx_pci_write_phy_register(pcr, addr, val);
248 int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
254 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
255 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x80);
258 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
271 rtsx_pci_read_register(pcr, PHYDATA0, &val1);
272 rtsx_pci_read_register(pcr, PHYDATA1, &val2);
281 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
283 if (pcr->ops->read_phy)
284 return pcr->ops->read_phy(pcr, addr, val);
286 return __rtsx_pci_read_phy_register(pcr, addr, val);
290 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
292 if (pcr->ops->stop_cmd)
293 return pcr->ops->stop_cmd(pcr);
295 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
296 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
298 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
299 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
303 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
308 u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
315 spin_lock_irqsave(&pcr->lock, flags);
316 ptr += pcr->ci;
317 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
320 pcr->ci++;
322 spin_unlock_irqrestore(&pcr->lock, flags);
326 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
330 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
332 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
335 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
339 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
347 spin_lock_irqsave(&pcr->lock, flags);
350 pcr->done = &trans_done;
351 pcr->trans_result = TRANS_NOT_READY;
354 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
356 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
359 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
361 spin_unlock_irqrestore(&pcr->lock, flags);
367 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
372 spin_lock_irqsave(&pcr->lock, flags);
373 if (pcr->trans_result == TRANS_RESULT_FAIL)
375 else if (pcr->trans_result == TRANS_RESULT_OK)
377 else if (pcr->trans_result == TRANS_NO_DEVICE)
379 spin_unlock_irqrestore(&pcr->lock, flags);
382 spin_lock_irqsave(&pcr->lock, flags);
383 pcr->done = NULL;
384 spin_unlock_irqrestore(&pcr->lock, flags);
387 rtsx_pci_stop_cmd(pcr);
389 if (pcr->finish_me)
390 complete(pcr->finish_me);
396 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
399 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
403 pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
408 if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5228)) {
418 pcr->sgi++;
421 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
426 pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg);
427 count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
430 pcr_dbg(pcr, "DMA mapping count: %d\n", count);
432 err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
434 rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
440 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
445 if (pcr->remove_pci)
451 return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
455 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
460 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
464 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
477 if (pcr->remove_pci)
484 pcr->sgi = 0;
488 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
491 spin_lock_irqsave(&pcr->lock, flags);
493 pcr->done = &trans_done;
494 pcr->trans_result = TRANS_NOT_READY;
496 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
497 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
499 spin_unlock_irqrestore(&pcr->lock, flags);
504 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
509 spin_lock_irqsave(&pcr->lock, flags);
510 if (pcr->trans_result == TRANS_RESULT_FAIL) {
512 if (pcr->dma_error_count < RTS_MAX_TIMES_FREQ_REDUCTION)
513 pcr->dma_error_count++;
516 else if (pcr->trans_result == TRANS_NO_DEVICE)
518 spin_unlock_irqrestore(&pcr->lock, flags);
521 spin_lock_irqsave(&pcr->lock, flags);
522 pcr->done = NULL;
523 spin_unlock_irqrestore(&pcr->lock, flags);
526 rtsx_pci_stop_cmd(pcr);
528 if (pcr->finish_me)
529 complete(pcr->finish_me);
535 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
548 rtsx_pci_init_cmd(pcr);
551 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
553 err = rtsx_pci_send_cmd(pcr, 250);
557 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
562 rtsx_pci_init_cmd(pcr);
565 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
567 err = rtsx_pci_send_cmd(pcr, 250);
572 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
578 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
591 rtsx_pci_init_cmd(pcr);
594 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
599 err = rtsx_pci_send_cmd(pcr, 250);
605 rtsx_pci_init_cmd(pcr);
608 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
613 err = rtsx_pci_send_cmd(pcr, 250);
622 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
624 rtsx_pci_init_cmd(pcr);
627 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
632 return rtsx_pci_send_cmd(pcr, 100);
635 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
640 tbl = pcr->sd_pull_ctl_enable_tbl;
642 tbl = pcr->ms_pull_ctl_enable_tbl;
646 return rtsx_pci_set_pull_ctl(pcr, tbl);
650 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
655 tbl = pcr->sd_pull_ctl_disable_tbl;
657 tbl = pcr->ms_pull_ctl_disable_tbl;
661 return rtsx_pci_set_pull_ctl(pcr, tbl);
665 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
667 struct rtsx_hw_param *hw_param = &pcr->hw_param;
669 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN
672 if (pcr->num_slots > 1)
673 pcr->bier |= MS_INT_EN;
676 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
678 pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
698 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
711 if (PCI_PID(pcr) == PID_5261)
712 return rts5261_pci_switch_clock(pcr, card_clock,
714 if (PCI_PID(pcr) == PID_5228)
715 return rts5228_pci_switch_clock(pcr, card_clock,
725 err = rtsx_pci_write_register(pcr, SD_CFG1,
732 pcr->dma_error_count &&
733 PCI_PID(pcr) == RTS5227_DEVICE_ID)
735 (pcr->dma_error_count * 20000000);
738 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
743 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
744 clk, pcr->cur_clock);
746 if (clk == pcr->cur_clock)
749 if (pcr->ops->conv_clk_and_div_n)
750 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
763 if (pcr->ops->conv_clk_and_div_n) {
764 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
766 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
773 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
780 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
782 rtsx_pci_init_cmd(pcr);
783 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
785 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
787 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
788 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
790 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
791 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
793 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
795 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
799 err = rtsx_pci_send_cmd(pcr, 2000);
805 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
809 pcr->cur_clock = clk;
814 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
816 if (pcr->ops->card_power_on)
817 return pcr->ops->card_power_on(pcr, card);
823 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
825 if (pcr->ops->card_power_off)
826 return pcr->ops->card_power_off(pcr, card);
832 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
839 if (!(pcr->flags & PCR_MS_PMOS)) {
843 if (pcr->card_exist & (~cd_mask[card]))
851 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
853 if (pcr->ops->switch_output_voltage)
854 return pcr->ops->switch_output_voltage(pcr, voltage);
860 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
864 val = rtsx_pci_readl(pcr, RTSX_BIPR);
865 if (pcr->ops->cd_deglitch)
866 val = pcr->ops->cd_deglitch(pcr);
872 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
876 pcr->finish_me = &finish;
879 if (pcr->done)
880 complete(pcr->done);
882 if (!pcr->remove_pci)
883 rtsx_pci_stop_cmd(pcr);
887 pcr->finish_me = NULL;
894 struct rtsx_pcr *pcr;
900 pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
902 pcr_dbg(pcr, "--> %s\n", __func__);
904 mutex_lock(&pcr->pcr_mutex);
905 spin_lock_irqsave(&pcr->lock, flags);
907 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
908 pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status);
911 card_inserted = pcr->card_inserted & irq_status;
912 card_removed = pcr->card_removed;
913 pcr->card_inserted = 0;
914 pcr->card_removed = 0;
916 spin_unlock_irqrestore(&pcr->lock, flags);
919 pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n",
922 if (pcr->ops->cd_deglitch)
923 card_inserted = pcr->ops->cd_deglitch(pcr);
927 pcr->card_exist |= card_inserted;
928 pcr->card_exist &= ~card_removed;
931 mutex_unlock(&pcr->pcr_mutex);
933 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
934 pcr->slots[RTSX_SD_CARD].card_event(
935 pcr->slots[RTSX_SD_CARD].p_dev);
936 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
937 pcr->slots[RTSX_MS_CARD].card_event(
938 pcr->slots[RTSX_MS_CARD].p_dev);
941 static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr)
943 if (pcr->ops->process_ocp) {
944 pcr->ops->process_ocp(pcr);
946 if (!pcr->option.ocp_en)
948 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
949 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
950 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
951 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
952 rtsx_pci_clear_ocpstat(pcr);
953 pcr->ocp_stat = 0;
958 static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr)
960 if (pcr->option.ocp_en)
961 rtsx_pci_process_ocp(pcr);
968 struct rtsx_pcr *pcr = dev_id;
971 if (!pcr)
974 spin_lock(&pcr->lock);
976 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
978 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
979 if ((int_reg & pcr->bier) == 0) {
980 spin_unlock(&pcr->lock);
984 spin_unlock(&pcr->lock);
988 int_reg &= (pcr->bier | 0x7FFFFF);
991 rtsx_pci_process_ocp_interrupt(pcr);
995 pcr->card_inserted |= SD_EXIST;
997 pcr->card_removed |= SD_EXIST;
998 pcr->card_inserted &= ~SD_EXIST;
999 if (PCI_PID(pcr) == PID_5261) {
1000 rtsx_pci_write_register(pcr, RTS5261_FW_STATUS,
1002 pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS;
1005 pcr->dma_error_count = 0;
1010 pcr->card_inserted |= MS_EXIST;
1012 pcr->card_removed |= MS_EXIST;
1013 pcr->card_inserted &= ~MS_EXIST;
1019 pcr->trans_result = TRANS_RESULT_FAIL;
1020 if (pcr->done)
1021 complete(pcr->done);
1023 pcr->trans_result = TRANS_RESULT_OK;
1024 if (pcr->done)
1025 complete(pcr->done);
1029 if ((pcr->card_inserted || pcr->card_removed) && !(int_reg & SD_OC_INT))
1030 schedule_delayed_work(&pcr->carddet_work,
1033 spin_unlock(&pcr->lock);
1037 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
1039 pcr_dbg(pcr, "%s: pcr->msi_en = %d, pci->irq = %d\n",
1040 __func__, pcr->msi_en, pcr->pci->irq);
1042 if (request_irq(pcr->pci->irq, rtsx_pci_isr,
1043 pcr->msi_en ? 0 : IRQF_SHARED,
1044 DRV_NAME_RTSX_PCI, pcr)) {
1045 dev_err(&(pcr->pci->dev),
1047 pcr->pci->irq);
1051 pcr->irq = pcr->pci->irq;
1052 pci_intx(pcr->pci, !pcr->msi_en);
1057 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr)
1060 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
1061 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
1062 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
1065 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
1068 rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
1071 static void __maybe_unused rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
1073 if (pcr->ops->turn_off_led)
1074 pcr->ops->turn_off_led(pcr);
1076 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1077 pcr->bier = 0;
1079 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1080 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
1082 if (pcr->ops->force_power_down)
1083 pcr->ops->force_power_down(pcr, pm_state, runtime);
1085 rtsx_base_force_power_down(pcr);
1088 void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr)
1092 if (pcr->ops->enable_ocp) {
1093 pcr->ops->enable_ocp(pcr);
1095 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
1096 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
1101 void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr)
1105 if (pcr->ops->disable_ocp) {
1106 pcr->ops->disable_ocp(pcr);
1108 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1109 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
1114 void rtsx_pci_init_ocp(struct rtsx_pcr *pcr)
1116 if (pcr->ops->init_ocp) {
1117 pcr->ops->init_ocp(pcr);
1119 struct rtsx_cr_option *option = &(pcr->option);
1124 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
1125 rtsx_pci_write_register(pcr, REG_OCPPARA1,
1127 rtsx_pci_write_register(pcr, REG_OCPPARA2,
1129 rtsx_pci_write_register(pcr, REG_OCPGLITCH,
1130 SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch);
1131 rtsx_pci_enable_ocp(pcr);
1136 int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
1138 if (pcr->ops->get_ocpstat)
1139 return pcr->ops->get_ocpstat(pcr, val);
1141 return rtsx_pci_read_register(pcr, REG_OCPSTAT, val);
1144 void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr)
1146 if (pcr->ops->clear_ocpstat) {
1147 pcr->ops->clear_ocpstat(pcr);
1152 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
1154 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1158 void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr)
1162 if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
1163 rtsx_pci_read_phy_register(pcr, 0x01, &val);
1165 rtsx_pci_write_phy_register(pcr, 0x01, val);
1167 rtsx_pci_write_register(pcr, REG_CFG_OOBS_OFF_TIMER, 0xFF, 0x32);
1168 rtsx_pci_write_register(pcr, REG_CFG_OOBS_ON_TIMER, 0xFF, 0x05);
1169 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x83);
1170 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0xDE);
1174 void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr)
1178 if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
1179 rtsx_pci_read_phy_register(pcr, 0x01, &val);
1181 rtsx_pci_write_phy_register(pcr, 0x01, val);
1183 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x03);
1184 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0x00);
1188 int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr)
1190 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1192 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
1193 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
1197 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
1202 int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr)
1204 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1207 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_MS_CARD);
1209 rtsx_pci_write_register(pcr, CARD_OE, MS_OUTPUT_EN, 0);
1210 rtsx_pci_card_power_off(pcr, RTSX_MS_CARD);
1215 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
1217 struct pci_dev *pdev = pcr->pci;
1220 if (PCI_PID(pcr) == PID_5228)
1221 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1, RTS5228_LDO1_SR_TIME_MASK,
1224 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
1226 rtsx_pci_enable_bus_int(pcr);
1229 if (PCI_PID(pcr) == PID_5261) {
1231 err = rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1233 err = rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
1236 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
1244 rtsx_disable_aspm(pcr);
1245 if (pcr->ops->optimize_phy) {
1246 err = pcr->ops->optimize_phy(pcr);
1251 rtsx_pci_init_cmd(pcr);
1254 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
1256 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
1258 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
1260 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
1262 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
1263 0xFF, pcr->card_drive_sel);
1265 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
1267 if (PCI_PID(pcr) == PID_5261)
1268 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1270 else if (PCI_PID(pcr) == PID_5228)
1271 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1274 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1277 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
1279 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
1284 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
1289 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
1295 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
1297 err = rtsx_pci_send_cmd(pcr, 100);
1301 switch (PCI_PID(pcr)) {
1308 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1);
1315 rtsx_pci_init_ocp(pcr);
1318 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
1323 if (pcr->ops->extra_init_hw) {
1324 err = pcr->ops->extra_init_hw(pcr);
1329 if (pcr->aspm_mode == ASPM_MODE_REG)
1330 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30);
1333 * So we need to initialize pcr->card_exist here.
1335 if (pcr->ops->cd_deglitch)
1336 pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1338 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1343 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1345 struct rtsx_cr_option *option = &(pcr->option);
1351 spin_lock_init(&pcr->lock);
1352 mutex_init(&pcr->pcr_mutex);
1354 switch (PCI_PID(pcr)) {
1357 rts5209_init_params(pcr);
1361 rts5229_init_params(pcr);
1365 rtl8411_init_params(pcr);
1369 rts5227_init_params(pcr);
1373 rts522a_init_params(pcr);
1377 rts5249_init_params(pcr);
1381 rts524a_init_params(pcr);
1385 rts525a_init_params(pcr);
1389 rtl8411b_init_params(pcr);
1393 rtl8402_init_params(pcr);
1397 rts5260_init_params(pcr);
1401 rts5261_init_params(pcr);
1405 rts5228_init_params(pcr);
1409 pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
1410 PCI_PID(pcr), pcr->ic_version);
1412 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1414 if (!pcr->slots)
1417 if (pcr->aspm_mode == ASPM_MODE_CFG) {
1418 pcie_capability_read_word(pcr->pci, PCI_EXP_LNKCTL, &cfg_val);
1420 pcr->aspm_enabled = true;
1422 pcr->aspm_enabled = false;
1424 } else if (pcr->aspm_mode == ASPM_MODE_REG) {
1425 rtsx_pci_read_register(pcr, ASPM_FORCE_CTL, &val);
1427 pcr->aspm_enabled = false;
1429 pcr->aspm_enabled = true;
1432 l1ss = pci_find_ext_capability(pcr->pci, PCI_EXT_CAP_ID_L1SS);
1434 pci_read_config_dword(pcr->pci, l1ss + PCI_L1SS_CTL1, &lval);
1437 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
1439 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
1442 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
1444 rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
1447 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
1449 rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
1452 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
1454 rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
1456 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cfg_val);
1464 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
1474 if (pcr->ops->fetch_vendor_settings)
1475 pcr->ops->fetch_vendor_settings(pcr);
1477 pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1478 pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1479 pcr->sd30_drive_sel_1v8);
1480 pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1481 pcr->sd30_drive_sel_3v3);
1482 pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n",
1483 pcr->card_drive_sel);
1484 pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags);
1486 pcr->state = PDEV_STAT_IDLE;
1487 err = rtsx_pci_init_hw(pcr);
1489 kfree(pcr->slots);
1499 struct rtsx_pcr *pcr;
1521 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1522 if (!pcr) {
1532 handle->pcr = pcr;
1536 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1538 pcr->id = ret;
1544 pcr->pci = pcidev;
1547 if (CHK_PCI_PID(pcr, 0x525A))
1551 pcr->remap_addr = ioremap(base, len);
1552 if (!pcr->remap_addr) {
1557 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1558 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1560 if (pcr->rtsx_resv_buf == NULL) {
1564 pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1565 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1566 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1567 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1568 pcr->card_inserted = 0;
1569 pcr->card_removed = 0;
1570 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1572 pcr->msi_en = msi_en;
1573 if (pcr->msi_en) {
1576 pcr->msi_en = false;
1579 ret = rtsx_pci_acquire_irq(pcr);
1584 synchronize_irq(pcr->irq);
1586 ret = rtsx_pci_init_chip(pcr);
1596 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1607 kfree(pcr->slots);
1609 free_irq(pcr->irq, (void *)pcr);
1611 if (pcr->msi_en)
1612 pci_disable_msi(pcr->pci);
1613 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1614 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1616 iounmap(pcr->remap_addr);
1619 idr_remove(&rtsx_pci_idr, pcr->id);
1624 kfree(pcr);
1636 struct rtsx_pcr *pcr = handle->pcr;
1638 pcr->remove_pci = true;
1643 /* Disable interrupts at the pcr level */
1644 spin_lock_irq(&pcr->lock);
1645 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1646 pcr->bier = 0;
1647 spin_unlock_irq(&pcr->lock);
1649 cancel_delayed_work_sync(&pcr->carddet_work);
1653 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1654 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1655 free_irq(pcr->irq, (void *)pcr);
1656 if (pcr->msi_en)
1657 pci_disable_msi(pcr->pci);
1658 iounmap(pcr->remap_addr);
1664 idr_remove(&rtsx_pci_idr, pcr->id);
1667 kfree(pcr->slots);
1668 kfree(pcr);
1680 struct rtsx_pcr *pcr = handle->pcr;
1684 cancel_delayed_work_sync(&pcr->carddet_work);
1686 mutex_lock(&pcr->pcr_mutex);
1688 rtsx_pci_power_off(pcr, HOST_ENTER_S3, false);
1690 mutex_unlock(&pcr->pcr_mutex);
1698 struct rtsx_pcr *pcr = handle->pcr;
1703 mutex_lock(&pcr->pcr_mutex);
1705 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1709 ret = rtsx_pci_init_hw(pcr);
1714 mutex_unlock(&pcr->pcr_mutex);
1720 static void rtsx_enable_aspm(struct rtsx_pcr *pcr)
1722 if (pcr->ops->set_aspm)
1723 pcr->ops->set_aspm(pcr, true);
1725 rtsx_comm_set_aspm(pcr, true);
1728 static void rtsx_comm_pm_power_saving(struct rtsx_pcr *pcr)
1730 struct rtsx_cr_option *option = &pcr->option;
1735 if (rtsx_check_dev_flag(pcr, L1_SNOOZE_TEST_EN))
1738 rtsx_set_ltr_latency(pcr, latency);
1741 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
1742 rtsx_set_l1off_sub_cfg_d0(pcr, 0);
1744 rtsx_enable_aspm(pcr);
1747 static void rtsx_pm_power_saving(struct rtsx_pcr *pcr)
1749 rtsx_comm_pm_power_saving(pcr);
1755 struct rtsx_pcr *pcr = handle->pcr;
1759 rtsx_pci_power_off(pcr, HOST_ENTER_S1, false);
1762 free_irq(pcr->irq, (void *)pcr);
1763 if (pcr->msi_en)
1764 pci_disable_msi(pcr->pci);
1771 struct rtsx_pcr *pcr = handle->pcr;
1775 mutex_lock(&pcr->pcr_mutex);
1777 pcr->state = PDEV_STAT_IDLE;
1779 if (pcr->ops->disable_auto_blink)
1780 pcr->ops->disable_auto_blink(pcr);
1781 if (pcr->ops->turn_off_led)
1782 pcr->ops->turn_off_led(pcr);
1784 rtsx_pm_power_saving(pcr);
1786 mutex_unlock(&pcr->pcr_mutex);
1788 if (pcr->rtd3_en)
1798 struct rtsx_pcr *pcr = handle->pcr;
1802 cancel_delayed_work_sync(&pcr->carddet_work);
1804 mutex_lock(&pcr->pcr_mutex);
1805 rtsx_pci_power_off(pcr, HOST_ENTER_S3, true);
1807 mutex_unlock(&pcr->pcr_mutex);
1816 struct rtsx_pcr *pcr = handle->pcr;
1820 mutex_lock(&pcr->pcr_mutex);
1822 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1824 rtsx_pci_init_hw(pcr);
1826 if (pcr->slots[RTSX_SD_CARD].p_dev != NULL) {
1827 pcr->slots[RTSX_SD_CARD].card_event(
1828 pcr->slots[RTSX_SD_CARD].p_dev);
1831 mutex_unlock(&pcr->pcr_mutex);