Lines Matching refs:pcr
18 static u8 rts5261_get_ic_version(struct rtsx_pcr *pcr)
22 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
26 static void rts5261_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
44 drive_sel = pcr->sd30_drive_sel_3v3;
47 drive_sel = pcr->sd30_drive_sel_1v8;
50 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
53 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
56 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
60 static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
63 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
64 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
65 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
69 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
73 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
75 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
76 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
80 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
83 rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
85 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
90 rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
94 static int rts5261_enable_auto_blink(struct rtsx_pcr *pcr)
96 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
100 static int rts5261_disable_auto_blink(struct rtsx_pcr *pcr)
102 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
106 static int rts5261_turn_on_led(struct rtsx_pcr *pcr)
108 return rtsx_pci_write_register(pcr, GPIO_CTL,
112 static int rts5261_turn_off_led(struct rtsx_pcr *pcr)
114 return rtsx_pci_write_register(pcr, GPIO_CTL,
144 static int rts5261_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
146 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
148 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
149 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
151 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
156 static int rts5261_card_power_on(struct rtsx_pcr *pcr, int card)
158 struct rtsx_cr_option *option = &pcr->option;
161 rtsx_pci_enable_ocp(pcr);
163 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
166 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG1,
168 rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
171 rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
176 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
179 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
182 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
184 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
185 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
189 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
190 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
194 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
195 pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
196 rts5261_sd_set_sample_push_timing_sd30(pcr);
201 static int rts5261_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
206 rtsx_pci_write_register(pcr, RTS5261_CARD_PWR_CTL,
211 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
213 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
217 rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
219 rtsx_pci_write_register(pcr, SD_PAD_CTL,
223 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
225 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
229 rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
231 rtsx_pci_write_register(pcr, SD_PAD_CTL,
239 rts5261_fill_driving(pcr, voltage);
244 static void rts5261_stop_cmd(struct rtsx_pcr *pcr)
246 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
247 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
248 rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
251 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
254 static void rts5261_card_before_power_off(struct rtsx_pcr *pcr)
256 rts5261_stop_cmd(pcr);
257 rts5261_switch_output_voltage(pcr, OUTPUT_3V3);
261 static void rts5261_enable_ocp(struct rtsx_pcr *pcr)
266 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
269 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
273 static void rts5261_disable_ocp(struct rtsx_pcr *pcr)
278 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
279 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
284 static int rts5261_card_power_off(struct rtsx_pcr *pcr, int card)
288 rts5261_card_before_power_off(pcr);
289 err = rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
292 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
294 if (pcr->option.ocp_en)
295 rtsx_pci_disable_ocp(pcr);
300 static void rts5261_init_ocp(struct rtsx_pcr *pcr)
302 struct rtsx_cr_option *option = &pcr->option;
307 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
311 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
314 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
319 val = pcr->hw_param.ocp_glitch;
320 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
322 rts5261_enable_ocp(pcr);
324 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
329 static void rts5261_clear_ocpstat(struct rtsx_pcr *pcr)
337 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
340 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
344 static void rts5261_process_ocp(struct rtsx_pcr *pcr)
346 if (!pcr->option.ocp_en)
349 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
351 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
352 rts5261_clear_ocpstat(pcr);
353 rts5261_card_power_off(pcr, RTSX_SD_CARD);
354 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
355 pcr->ocp_stat = 0;
360 static void rts5261_init_from_hw(struct rtsx_pcr *pcr)
362 struct pci_dev *pdev = pcr->pci;
367 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
371 rtsx_pci_write_register(pcr, RTS5261_EFUSE_ADDR,
373 rtsx_pci_write_register(pcr, RTS5261_EFUSE_CTL,
379 rtsx_pci_read_register(pcr, RTS5261_EFUSE_CTL, &tmp);
383 rtsx_pci_read_register(pcr, RTS5261_EFUSE_READ_DATA, &tmp);
385 pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);
388 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, lval2);
392 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
394 pcr_dbg(pcr, "Disable efuse por!\n");
415 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg2, lval2);
419 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
420 pcr_dbg(pcr, "skip fetch vendor setting\n");
425 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
427 pcr->rtd3_en = rts5261_reg_to_rtd3(lval2);
430 pcr->flags |= PCR_REVERSE_SOCKET;
433 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg1, lval1);
435 pcr->aspm_en = rts5261_reg_to_aspm(lval1);
436 pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(lval1);
437 pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(lval1);
441 rtsx_pci_write_register(pcr, 0xFF0C, 0xFF, (u8)(lval1 & 0xFF));
442 rtsx_pci_write_register(pcr, 0xFF0D, 0xFF, (u8)((lval1 >> 8) & 0xFF));
443 rtsx_pci_write_register(pcr, 0xFF0E, 0xFF, (u8)((lval1 >> 16) & 0xFF));
444 rtsx_pci_write_register(pcr, 0xFF0F, 0xFF, (u8)((lval1 >> 24) & 0xFF));
445 rtsx_pci_write_register(pcr, 0xFF10, 0xFF, (u8)(lval2 & 0xFF));
446 rtsx_pci_write_register(pcr, 0xFF11, 0xFF, (u8)((lval2 >> 8) & 0xFF));
447 rtsx_pci_write_register(pcr, 0xFF12, 0xFF, (u8)((lval2 >> 16) & 0xFF));
455 static void rts5261_init_from_cfg(struct rtsx_pcr *pcr)
457 struct rtsx_cr_option *option = &pcr->option;
461 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
465 static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
467 struct rtsx_cr_option *option = &pcr->option;
470 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
473 rts5261_init_from_cfg(pcr);
474 rts5261_init_from_hw(pcr);
477 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
479 rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
481 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
483 if (is_version_higher_than(pcr, PID_5261, IC_VER_B)) {
484 val = rtsx_pci_readl(pcr, RTSX_DUM_REG);
485 rtsx_pci_writel(pcr, RTSX_DUM_REG, val | 0x1);
487 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
491 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
493 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
496 rtsx_pci_write_register(pcr, PCLK_CTL,
499 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
500 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
503 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
506 rts5261_fill_driving(pcr, OUTPUT_3V3);
508 if (pcr->flags & PCR_REVERSE_SOCKET)
509 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
511 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
518 rtsx_pci_write_register(pcr, PETXCFG,
521 rtsx_pci_write_register(pcr, PETXCFG,
524 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
526 if (pcr->rtd3_en) {
527 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);
528 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
532 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
533 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
536 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);
539 rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
545 static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable)
550 if (pcr->aspm_enabled == enable)
553 val |= (pcr->aspm_en & 0x02);
554 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
555 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
556 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
557 pcr->aspm_enabled = enable;
560 static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable)
565 if (pcr->aspm_enabled == enable)
568 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
570 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
571 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
573 pcr->aspm_enabled = enable;
576 static void rts5261_set_aspm(struct rtsx_pcr *pcr, bool enable)
579 rts5261_enable_aspm(pcr, true);
581 rts5261_disable_aspm(pcr, false);
584 static void rts5261_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
586 struct rtsx_cr_option *option = &pcr->option;
590 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
591 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
603 rtsx_set_l1off_sub(pcr, val);
631 int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
646 if (is_version_higher_than(pcr, PID_5261, IC_VER_C)) {
656 err = rtsx_pci_write_register(pcr, SD_CFG1,
662 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
667 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
668 clk, pcr->cur_clock);
670 if (clk == pcr->cur_clock)
673 if (pcr->ops->conv_clk_and_div_n)
674 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
686 if (pcr->ops->conv_clk_and_div_n) {
687 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
689 n = pcr->ops->conv_clk_and_div_n(dbl_clk,
698 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
724 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
726 rtsx_pci_init_cmd(pcr);
727 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
729 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
731 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
732 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
734 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
735 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
737 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
739 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
741 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
743 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
747 err = rtsx_pci_send_cmd(pcr, 2000);
753 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
757 pcr->cur_clock = clk;
762 void rts5261_init_params(struct rtsx_pcr *pcr)
764 struct rtsx_cr_option *option = &pcr->option;
765 struct rtsx_hw_param *hw_param = &pcr->hw_param;
768 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
769 rtsx_pci_read_register(pcr, RTS5261_FW_STATUS, &val);
771 pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS;
772 pcr->num_slots = 1;
773 pcr->ops = &rts5261_pcr_ops;
775 pcr->flags = 0;
776 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
777 pcr->sd30_drive_sel_1v8 = 0x00;
778 pcr->sd30_drive_sel_3v3 = 0x00;
779 pcr->aspm_en = ASPM_L1_EN;
780 pcr->aspm_mode = ASPM_MODE_REG;
781 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11);
782 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
784 pcr->ic_version = rts5261_get_ic_version(pcr);
785 pcr->sd_pull_ctl_enable_tbl = rts5261_sd_pull_ctl_enable_tbl;
786 pcr->sd_pull_ctl_disable_tbl = rts5261_sd_pull_ctl_disable_tbl;
788 pcr->reg_pm_ctrl3 = RTS5261_AUTOLOAD_CFG3;