Lines Matching refs:pcr
16 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
20 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
24 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
42 drive_sel = pcr->sd30_drive_sel_3v3;
45 drive_sel = pcr->sd30_drive_sel_1v8;
48 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
50 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
52 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
56 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
58 struct pci_dev *pdev = pcr->pci;
62 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
65 pcr_dbg(pcr, "skip fetch vendor setting\n");
69 pcr->aspm_en = rtsx_reg_to_aspm(reg);
70 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
71 pcr->card_drive_sel &= 0x3F;
72 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
75 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
77 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
78 pcr->rtd3_en = rtsx_reg_to_rtd3_uhsii(reg);
81 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
82 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
84 pcr->flags |= PCR_REVERSE_SOCKET;
87 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
89 struct rtsx_cr_option *option = &(pcr->option);
91 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
92 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
94 rtsx_pci_disable_oobs_polling(pcr);
96 rtsx_pci_enable_oobs_polling(pcr);
101 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
105 static void rts52xa_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
108 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
109 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
110 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
113 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
117 rtsx_pci_write_register(pcr, RTS524A_AUTOLOAD_CFG1,
119 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00);
120 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20);
123 rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
126 static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr)
134 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
138 pcr_dbg(pcr, "Enable efuse por!");
139 pcr_dbg(pcr, "save efuse to autoload");
141 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00);
142 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
146 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
150 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
156 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
158 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
162 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
166 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
167 rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val);
170 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
171 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
172 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
173 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
178 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
181 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
183 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
187 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
191 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
192 rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val);
194 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80);
195 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
197 pcr_dbg(pcr, "Disable efuse por!");
200 static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr)
204 rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val);
206 rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val);
208 rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG,
211 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
214 pcr_dbg(pcr, "Power ON efuse!");
216 rts52xa_save_content_from_efuse(pcr);
218 rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val);
220 rts52xa_save_content_from_efuse(pcr);
223 pcr_dbg(pcr, "Load from autoload");
224 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80);
225 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
226 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
227 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
228 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
232 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
234 struct rtsx_cr_option *option = &(pcr->option);
236 rts5249_init_from_cfg(pcr);
238 rtsx_pci_init_cmd(pcr);
240 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
241 rts52xa_save_content_to_autoload_space(pcr);
244 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
246 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
248 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
250 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
251 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
253 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
255 rts5249_fill_driving(pcr, OUTPUT_3V3);
256 if (pcr->flags & PCR_REVERSE_SOCKET)
257 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
259 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
261 rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
263 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
264 rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN);
265 rtsx_pci_write_register(pcr, RTS524A_AUTOLOAD_CFG1,
269 if (pcr->rtd3_en) {
270 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
271 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x01);
272 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x30);
274 rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x01);
275 rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x33);
278 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
279 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00);
280 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20);
282 rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30);
283 rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00);
293 rtsx_pci_write_register(pcr, PETXCFG,
296 rtsx_pci_write_register(pcr, PETXCFG,
299 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
300 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
301 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
303 pcr_dbg(pcr, "Power OFF efuse!");
309 static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
313 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
317 err = rtsx_pci_write_phy_register(pcr, PHY_REV,
328 err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
334 err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
341 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
348 err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
355 err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
359 err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
363 err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
369 return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
375 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
377 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
380 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
382 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
385 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
387 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
390 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
392 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
395 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
398 struct rtsx_cr_option *option = &pcr->option;
401 rtsx_pci_enable_ocp(pcr);
403 rtsx_pci_init_cmd(pcr);
404 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
406 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
408 err = rtsx_pci_send_cmd(pcr, 100);
414 rtsx_pci_init_cmd(pcr);
415 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
417 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
419 return rtsx_pci_send_cmd(pcr, 100);
422 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
424 struct rtsx_cr_option *option = &pcr->option;
427 rtsx_pci_disable_ocp(pcr);
429 rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF);
431 rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00);
435 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
442 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
449 if (CHK_PCI_PID(pcr, 0x5249)) {
450 err = rtsx_pci_update_phy(pcr, PHY_BACR,
457 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
463 pcr_dbg(pcr, "unknown output voltage %d\n", voltage);
468 rtsx_pci_init_cmd(pcr);
469 rts5249_fill_driving(pcr, voltage);
470 return rtsx_pci_send_cmd(pcr, 100);
538 void rts5249_init_params(struct rtsx_pcr *pcr)
540 struct rtsx_cr_option *option = &(pcr->option);
542 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
543 pcr->num_slots = 2;
544 pcr->ops = &rts5249_pcr_ops;
546 pcr->flags = 0;
547 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
548 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
549 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
550 pcr->aspm_en = ASPM_L1_EN;
551 pcr->aspm_mode = ASPM_MODE_CFG;
552 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
553 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
555 pcr->ic_version = rts5249_get_ic_version(pcr);
556 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
557 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
558 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
559 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
561 pcr->reg_pm_ctrl3 = PM_CTRL3;
577 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
581 return __rtsx_pci_write_phy_register(pcr, addr, val);
584 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
588 return __rtsx_pci_read_phy_register(pcr, addr, val);
591 static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
595 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
600 rtsx_pci_write_phy_register(pcr, PHY_PCR,
603 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
606 if (is_version(pcr, 0x524A, IC_VER_A)) {
607 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
609 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
612 rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
615 rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
617 rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
627 rtsx_pci_write_phy_register(pcr, PHY_ANA08,
634 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
636 rts5249_extra_init_hw(pcr);
638 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
640 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
641 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
643 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
644 if (is_version(pcr, 0x524A, IC_VER_A)) {
645 rtsx_pci_write_register(pcr, LDO_DV18_CFG,
647 rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
649 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
651 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
653 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
655 rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
662 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
664 struct rtsx_cr_option *option = &(pcr->option);
666 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
671 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
672 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
685 if (rtsx_check_dev_flag(pcr,
693 rtsx_set_l1off_sub(pcr, val);
713 void rts524a_init_params(struct rtsx_pcr *pcr)
715 rts5249_init_params(pcr);
716 pcr->aspm_mode = ASPM_MODE_REG;
717 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
718 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
719 pcr->option.ltr_l1off_snooze_sspwrgate =
722 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
723 pcr->ops = &rts524a_pcr_ops;
725 pcr->option.ocp_en = 1;
726 if (pcr->option.ocp_en)
727 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
728 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
729 pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800;
733 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
735 rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
737 return rtsx_base_card_power_on(pcr, card);
740 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
744 rtsx_pci_write_register(pcr, LDO_CONFIG2,
746 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
749 rtsx_pci_write_register(pcr, LDO_CONFIG2,
751 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
758 rtsx_pci_init_cmd(pcr);
759 rts5249_fill_driving(pcr, voltage);
760 return rtsx_pci_send_cmd(pcr, 100);
763 static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
767 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
772 rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
777 rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
781 if (is_version(pcr, 0x525A, IC_VER_A))
782 rtsx_pci_write_phy_register(pcr, _PHY_REV0,
789 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
791 rts5249_extra_init_hw(pcr);
793 rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD);
795 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
796 if (is_version(pcr, 0x525A, IC_VER_A)) {
797 rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
799 rtsx_pci_write_register(pcr, RREF_CFG,
801 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
803 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
805 rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
807 rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
809 rtsx_pci_write_register(pcr, OOBS_CONFIG,
831 void rts525a_init_params(struct rtsx_pcr *pcr)
833 rts5249_init_params(pcr);
834 pcr->aspm_mode = ASPM_MODE_REG;
835 pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
836 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
837 pcr->option.ltr_l1off_snooze_sspwrgate =
840 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
841 pcr->ops = &rts525a_pcr_ops;
843 pcr->option.ocp_en = 1;
844 if (pcr->option.ocp_en)
845 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
846 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
847 pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800;