Lines Matching refs:val
21 u8 val;
23 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
24 return val & IC_VERSION_MASK;
232 u16 val = 0;
239 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
240 val |= PHY_TUNE_SDBUS_33;
241 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
251 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
252 val &= ~PHY_TUNE_SDBUS_33;
253 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
290 u8 val = 0;
292 val = SD_OCP_INT_EN | SD_DETECT_EN;
293 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
329 u8 mask, val;
342 rtsx_pci_read_register(pcr, RTS5228_LDO1_CFG0, &val);
345 val = pcr->hw_param.ocp_glitch;
346 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
359 u8 val = 0;
362 val = SD_OCP_INT_CLR | SD_OC_CLR;
364 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
468 u8 mask, val;
474 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
475 val |= (pcr->aspm_en & 0x02);
476 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
484 u8 mask, val;
492 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
493 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
511 u8 val = 0;
519 val = option->ltr_l1off_snooze_sspwrgate;
523 val = option->ltr_l1off_sspwrgate;
526 rtsx_set_l1off_sub(pcr, val);