Lines Matching refs:pcr
19 static u8 rts5228_get_ic_version(struct rtsx_pcr *pcr)
23 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
27 static void rts5228_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
45 drive_sel = pcr->sd30_drive_sel_3v3;
48 drive_sel = pcr->sd30_drive_sel_1v8;
51 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
54 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
57 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
61 static void rtsx5228_fetch_vendor_settings(struct rtsx_pcr *pcr)
63 struct pci_dev *pdev = pcr->pci;
68 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
71 pcr_dbg(pcr, "skip fetch vendor setting\n");
74 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
75 pcr->aspm_en = rtsx_reg_to_aspm(reg);
79 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
81 pcr->rtd3_en = rtsx_reg_to_rtd3(reg);
83 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
84 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
86 pcr->flags |= PCR_REVERSE_SOCKET;
89 static int rts5228_optimize_phy(struct rtsx_pcr *pcr)
91 return rtsx_pci_write_phy_register(pcr, 0x07, 0x8F40);
94 static void rts5228_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
97 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
98 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
99 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
102 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
106 rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1,
108 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
109 rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
113 rtsx_pci_write_register(pcr, FPDCTL,
117 static int rts5228_enable_auto_blink(struct rtsx_pcr *pcr)
119 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
123 static int rts5228_disable_auto_blink(struct rtsx_pcr *pcr)
125 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
129 static int rts5228_turn_on_led(struct rtsx_pcr *pcr)
131 return rtsx_pci_write_register(pcr, GPIO_CTL,
135 static int rts5228_turn_off_led(struct rtsx_pcr *pcr)
137 return rtsx_pci_write_register(pcr, GPIO_CTL,
167 static int rts5228_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
169 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
171 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
172 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
174 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
179 static int rts5228_card_power_on(struct rtsx_pcr *pcr, int card)
181 struct rtsx_cr_option *option = &pcr->option;
184 rtsx_pci_enable_ocp(pcr);
186 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
189 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1,
192 rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
195 rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
199 rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
204 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
207 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
210 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
212 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
213 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
217 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
218 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
222 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
223 pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
224 rts5228_sd_set_sample_push_timing_sd30(pcr);
229 static int rts5228_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
234 rtsx_pci_write_register(pcr, RTS5228_CARD_PWR_CTL,
239 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
241 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
245 rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG,
247 rtsx_pci_write_register(pcr, SD_PAD_CTL,
251 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
253 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
257 rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG,
259 rtsx_pci_write_register(pcr, SD_PAD_CTL,
267 rts5228_fill_driving(pcr, voltage);
272 static void rts5228_stop_cmd(struct rtsx_pcr *pcr)
274 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
275 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
276 rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
279 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
282 static void rts5228_card_before_power_off(struct rtsx_pcr *pcr)
284 rts5228_stop_cmd(pcr);
285 rts5228_switch_output_voltage(pcr, OUTPUT_3V3);
288 static void rts5228_enable_ocp(struct rtsx_pcr *pcr)
293 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
294 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
299 static void rts5228_disable_ocp(struct rtsx_pcr *pcr)
304 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
305 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
309 static int rts5228_card_power_off(struct rtsx_pcr *pcr, int card)
313 rts5228_card_before_power_off(pcr);
314 err = rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
316 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, CFG_SD_POW_AUTO_PD, 0);
318 if (pcr->option.ocp_en)
319 rtsx_pci_disable_ocp(pcr);
324 static void rts5228_init_ocp(struct rtsx_pcr *pcr)
326 struct rtsx_cr_option *option = &pcr->option;
331 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
335 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
338 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
342 rtsx_pci_read_register(pcr, RTS5228_LDO1_CFG0, &val);
345 val = pcr->hw_param.ocp_glitch;
346 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
348 rts5228_enable_ocp(pcr);
351 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
356 static void rts5228_clear_ocpstat(struct rtsx_pcr *pcr)
364 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
367 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
371 static void rts5228_process_ocp(struct rtsx_pcr *pcr)
373 if (!pcr->option.ocp_en)
376 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
378 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
379 rts5228_clear_ocpstat(pcr);
380 rts5228_card_power_off(pcr, RTSX_SD_CARD);
381 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
382 pcr->ocp_stat = 0;
387 static void rts5228_init_from_cfg(struct rtsx_pcr *pcr)
389 struct rtsx_cr_option *option = &pcr->option;
391 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
393 rtsx_pci_disable_oobs_polling(pcr);
395 rtsx_pci_enable_oobs_polling(pcr);
397 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
401 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
405 static int rts5228_extra_init_hw(struct rtsx_pcr *pcr)
407 struct rtsx_cr_option *option = &pcr->option;
409 rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1,
412 rts5228_init_from_cfg(pcr);
414 rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
416 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
418 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
421 rtsx_pci_write_register(pcr, PCLK_CTL,
424 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
425 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
428 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
431 rts5228_fill_driving(pcr, OUTPUT_3V3);
433 if (pcr->flags & PCR_REVERSE_SOCKET)
434 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
436 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
443 rtsx_pci_write_register(pcr, PETXCFG,
446 rtsx_pci_write_register(pcr, PETXCFG,
449 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
451 if (pcr->rtd3_en) {
452 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);
453 rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
457 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
458 rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
461 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);
466 static void rts5228_enable_aspm(struct rtsx_pcr *pcr, bool enable)
470 if (pcr->aspm_enabled == enable)
475 val |= (pcr->aspm_en & 0x02);
476 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
477 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
478 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
479 pcr->aspm_enabled = enable;
482 static void rts5228_disable_aspm(struct rtsx_pcr *pcr, bool enable)
486 if (pcr->aspm_enabled == enable)
489 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
493 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
494 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
496 pcr->aspm_enabled = enable;
499 static void rts5228_set_aspm(struct rtsx_pcr *pcr, bool enable)
502 rts5228_enable_aspm(pcr, true);
504 rts5228_disable_aspm(pcr, false);
507 static void rts5228_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
509 struct rtsx_cr_option *option = &pcr->option;
513 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
514 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
526 rtsx_set_l1off_sub(pcr, val);
557 int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
577 err = rtsx_pci_write_register(pcr, SD_CFG1,
583 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
588 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
589 clk, pcr->cur_clock);
591 if (clk == pcr->cur_clock)
594 if (pcr->ops->conv_clk_and_div_n)
595 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
607 if (pcr->ops->conv_clk_and_div_n) {
608 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
610 n = pcr->ops->conv_clk_and_div_n(dbl_clk,
619 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
645 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
647 rtsx_pci_init_cmd(pcr);
648 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
650 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
652 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
653 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
655 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
656 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
658 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
660 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
662 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
664 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
668 err = rtsx_pci_send_cmd(pcr, 2000);
674 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
678 pcr->cur_clock = clk;
683 void rts5228_init_params(struct rtsx_pcr *pcr)
685 struct rtsx_cr_option *option = &pcr->option;
686 struct rtsx_hw_param *hw_param = &pcr->hw_param;
688 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
689 pcr->num_slots = 1;
690 pcr->ops = &rts5228_pcr_ops;
692 pcr->flags = 0;
693 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
694 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
695 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
696 pcr->aspm_en = ASPM_L1_EN;
697 pcr->aspm_mode = ASPM_MODE_REG;
698 pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11);
699 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
701 pcr->ic_version = rts5228_get_ic_version(pcr);
702 pcr->sd_pull_ctl_enable_tbl = rts5228_sd_pull_ctl_enable_tbl;
703 pcr->sd_pull_ctl_disable_tbl = rts5228_sd_pull_ctl_disable_tbl;
705 pcr->reg_pm_ctrl3 = RTS5228_AUTOLOAD_CFG3;