Lines Matching defs:pcr
16 static u8 rts5209_get_ic_version(struct rtsx_pcr *pcr)
20 val = rtsx_pci_readb(pcr, 0x1C);
24 static void rts5209_fetch_vendor_settings(struct rtsx_pcr *pcr)
26 struct pci_dev *pdev = pcr->pci;
30 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
34 pcr->flags |= PCR_MS_PMOS;
35 pcr->aspm_en = rts5209_reg_to_aspm(reg);
39 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
42 pcr->sd30_drive_sel_1v8 =
44 pcr->sd30_drive_sel_3v3 =
46 pcr->card_drive_sel = rts5209_reg_to_card_drive_sel(reg);
50 static void rts5209_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
52 rtsx_pci_write_register(pcr, FPDCTL, 0x07, 0x07);
55 static int rts5209_extra_init_hw(struct rtsx_pcr *pcr)
57 rtsx_pci_init_cmd(pcr);
60 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO, 0xFF, 0x03);
62 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
64 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
66 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO_DIR, 0xFF, 0x03);
68 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
69 0xFF, pcr->sd30_drive_sel_3v3);
71 return rtsx_pci_send_cmd(pcr, 100);
74 static int rts5209_optimize_phy(struct rtsx_pcr *pcr)
76 return rtsx_pci_write_phy_register(pcr, 0x00, 0xB966);
79 static int rts5209_turn_on_led(struct rtsx_pcr *pcr)
81 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00);
84 static int rts5209_turn_off_led(struct rtsx_pcr *pcr)
86 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01);
89 static int rts5209_enable_auto_blink(struct rtsx_pcr *pcr)
91 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D);
94 static int rts5209_disable_auto_blink(struct rtsx_pcr *pcr)
96 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00);
99 static int rts5209_card_power_on(struct rtsx_pcr *pcr, int card)
108 if ((pcr->flags & PCR_MS_PMOS) && (card == RTSX_MS_CARD)) {
114 rtsx_pci_init_cmd(pcr);
115 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
117 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
119 err = rtsx_pci_send_cmd(pcr, 100);
126 rtsx_pci_init_cmd(pcr);
127 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, pwr_mask, pwr_on);
128 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
130 return rtsx_pci_send_cmd(pcr, 100);
133 static int rts5209_card_power_off(struct rtsx_pcr *pcr, int card)
140 if ((pcr->flags & PCR_MS_PMOS) && (card == RTSX_MS_CARD)) {
145 rtsx_pci_init_cmd(pcr);
146 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
148 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
150 return rtsx_pci_send_cmd(pcr, 100);
153 static int rts5209_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
158 err = rtsx_pci_write_register(pcr,
159 SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3);
162 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
166 err = rtsx_pci_write_register(pcr,
167 SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8);
170 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C40 | 0x24);
246 void rts5209_init_params(struct rtsx_pcr *pcr)
248 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 |
250 pcr->num_slots = 2;
251 pcr->ops = &rts5209_pcr_ops;
253 pcr->flags = 0;
254 pcr->card_drive_sel = RTS5209_CARD_DRIVE_DEFAULT;
255 pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
256 pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
257 pcr->aspm_en = ASPM_L1_EN;
258 pcr->aspm_mode = ASPM_MODE_CFG;
259 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 16);
260 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
262 pcr->ic_version = rts5209_get_ic_version(pcr);
263 pcr->sd_pull_ctl_enable_tbl = rts5209_sd_pull_ctl_enable_tbl;
264 pcr->sd_pull_ctl_disable_tbl = rts5209_sd_pull_ctl_disable_tbl;
265 pcr->ms_pull_ctl_enable_tbl = rts5209_ms_pull_ctl_enable_tbl;
266 pcr->ms_pull_ctl_disable_tbl = rts5209_ms_pull_ctl_disable_tbl;