Lines Matching refs:pcr
18 static u8 rtl8411_get_ic_version(struct rtsx_pcr *pcr)
22 rtsx_pci_read_register(pcr, SYS_VER, &val);
26 static int rtl8411b_is_qfn48(struct rtsx_pcr *pcr)
30 rtsx_pci_read_register(pcr, RTL8411B_PACKAGE_MODE, &val);
38 static void rtl8411_fetch_vendor_settings(struct rtsx_pcr *pcr)
40 struct pci_dev *pdev = pcr->pci;
45 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1);
50 pcr->aspm_en = rtsx_reg_to_aspm(reg1);
51 pcr->sd30_drive_sel_1v8 =
53 pcr->card_drive_sel &= 0x3F;
54 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg1);
57 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG3, reg3);
58 pcr->sd30_drive_sel_3v3 = rtl8411_reg_to_sd30_drive_sel_3v3(reg3);
61 static void rtl8411b_fetch_vendor_settings(struct rtsx_pcr *pcr)
63 struct pci_dev *pdev = pcr->pci;
67 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
72 pcr->aspm_en = rtsx_reg_to_aspm(reg);
73 pcr->sd30_drive_sel_1v8 =
75 pcr->sd30_drive_sel_3v3 =
79 static void rtl8411_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
81 rtsx_pci_write_register(pcr, FPDCTL, 0x07, 0x07);
84 static int rtl8411_extra_init_hw(struct rtsx_pcr *pcr)
86 rtsx_pci_init_cmd(pcr);
88 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
89 0xFF, pcr->sd30_drive_sel_3v3);
90 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL,
93 return rtsx_pci_send_cmd(pcr, 100);
96 static int rtl8411b_extra_init_hw(struct rtsx_pcr *pcr)
98 rtsx_pci_init_cmd(pcr);
100 if (rtl8411b_is_qfn48(pcr))
101 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
103 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
104 0xFF, pcr->sd30_drive_sel_3v3);
105 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL,
107 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, FUNC_FORCE_CTL,
110 return rtsx_pci_send_cmd(pcr, 100);
113 static int rtl8411_turn_on_led(struct rtsx_pcr *pcr)
115 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00);
118 static int rtl8411_turn_off_led(struct rtsx_pcr *pcr)
120 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01);
123 static int rtl8411_enable_auto_blink(struct rtsx_pcr *pcr)
125 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D);
128 static int rtl8411_disable_auto_blink(struct rtsx_pcr *pcr)
130 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00);
133 static int rtl8411_card_power_on(struct rtsx_pcr *pcr, int card)
137 rtsx_pci_init_cmd(pcr);
138 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
140 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_CTL,
142 err = rtsx_pci_send_cmd(pcr, 100);
149 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
156 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
163 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
168 return rtsx_pci_write_register(pcr, LDO_CTL, BPP_LDO_POWB, BPP_LDO_ON);
171 static int rtl8411_card_power_off(struct rtsx_pcr *pcr, int card)
175 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
180 return rtsx_pci_write_register(pcr, LDO_CTL,
184 static int rtl8411_do_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage,
192 err = rtsx_pci_write_register(pcr,
193 SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3);
198 err = rtsx_pci_write_register(pcr,
199 SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8);
207 return rtsx_pci_write_register(pcr, LDO_CTL, mask, val);
210 static int rtl8411_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
212 return rtl8411_do_switch_output_voltage(pcr, voltage,
216 static int rtl8402_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
218 return rtl8411_do_switch_output_voltage(pcr, voltage,
222 static unsigned int rtl8411_cd_deglitch(struct rtsx_pcr *pcr)
226 card_exist = rtsx_pci_readl(pcr, RTSX_BIPR);
230 rtsx_pci_write_register(pcr, CD_PAD_CTL,
233 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x00);
238 rtsx_pci_write_register(pcr, CARD_PWR_CTL,
242 card_exist = rtsx_pci_readl(pcr, RTSX_BIPR);
250 rtsx_pci_write_register(pcr, CARD_PWR_CTL,
253 pcr_dbg(pcr, "After CD deglitch, card_exist = 0x%x\n",
259 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x40);
260 rtsx_pci_write_register(pcr, CD_PAD_CTL,
264 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x80);
265 rtsx_pci_write_register(pcr, CD_PAD_CTL,
462 static void rtl8411_init_common_params(struct rtsx_pcr *pcr)
464 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
465 pcr->num_slots = 2;
466 pcr->flags = 0;
467 pcr->card_drive_sel = RTL8411_CARD_DRIVE_DEFAULT;
468 pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
469 pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
470 pcr->aspm_en = ASPM_L1_EN;
471 pcr->aspm_mode = ASPM_MODE_CFG;
472 pcr->tx_initial_phase = SET_CLOCK_PHASE(23, 7, 14);
473 pcr->rx_initial_phase = SET_CLOCK_PHASE(4, 3, 10);
474 pcr->ic_version = rtl8411_get_ic_version(pcr);
477 void rtl8411_init_params(struct rtsx_pcr *pcr)
479 rtl8411_init_common_params(pcr);
480 pcr->ops = &rtl8411_pcr_ops;
481 set_pull_ctrl_tables(pcr, rtl8411);
484 void rtl8411b_init_params(struct rtsx_pcr *pcr)
486 rtl8411_init_common_params(pcr);
487 pcr->ops = &rtl8411b_pcr_ops;
488 if (rtl8411b_is_qfn48(pcr))
489 set_pull_ctrl_tables(pcr, rtl8411b_qfn48);
491 set_pull_ctrl_tables(pcr, rtl8411b_qfn64);
494 void rtl8402_init_params(struct rtsx_pcr *pcr)
496 rtl8411_init_common_params(pcr);
497 pcr->ops = &rtl8402_pcr_ops;
498 set_pull_ctrl_tables(pcr, rtl8411);