Lines Matching defs:clock
130 * Print out the current clock configuration for the device
320 unsigned long clock;
326 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
359 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
365 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
377 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
378 gate, clock, mode);
389 /* clock value structure. */
399 * Calculates the nearest discrete clock frequency that
400 * can be achieved with the specified input clock.
405 struct sm501_clock *clock,
421 /* Calculate difference to requested clock */
430 clock->mclk = mclk;
431 clock->divider = divider;
432 clock->shift = shift;
443 * Calculates the nearest discrete clock frequency that can be
449 struct sm501_clock *clock,
465 if (sm501_calc_clock(freq, clock, max_div,
467 clock->m = m;
468 clock->n = n;
469 clock->k = k;
475 /* Return best clock. */
476 return clock->mclk / (clock->divider << clock->shift);
481 * Calculates the nearest discrete clock frequency that can be
487 struct sm501_clock *clock,
495 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
498 /* Return best clock. */
499 return clock->mclk / (clock->divider << clock->shift);
504 * set one of the four clock sources to the closest available frequency to
515 unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
528 /* This clock is divided in half so to achieve the
530 * 2. This clock also has an additional pre divisor */
557 /* This clock is divided in half so to achieve the
588 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
590 clock = clock & ~(0xFF << clksrc);
591 clock |= reg<<clksrc;
598 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
604 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
621 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
622 gate, clock, mode);
636 * finds the closest available frequency for a given clock