Lines Matching defs:menelaus_write_reg

171 static int menelaus_write_reg(int reg, u8 value)
198 return menelaus_write_reg(MENELAUS_INT_MASK2,
202 return menelaus_write_reg(MENELAUS_INT_MASK1,
212 return menelaus_write_reg(MENELAUS_INT_MASK2,
216 return menelaus_write_reg(MENELAUS_INT_MASK1,
224 return menelaus_write_reg(MENELAUS_INT_ACK2, 1 << (irq - 8));
226 return menelaus_write_reg(MENELAUS_INT_ACK1, 1 << irq);
309 ret = menelaus_write_reg(MENELAUS_MCT_CTRL1, val);
329 ret = menelaus_write_reg(MENELAUS_GPIO_CTRL, ret);
362 ret = menelaus_write_reg(MENELAUS_MCT_CTRL2, val);
385 ret = menelaus_write_reg(MENELAUS_MCT_CTRL2, b);
391 ret = menelaus_write_reg(MENELAUS_MCT_CTRL3, val);
467 ret = menelaus_write_reg(vtg->vtg_reg, val);
470 ret = menelaus_write_reg(vtg->mode_reg, mode);
540 ret = menelaus_write_reg(MENELAUS_VCORE_CTRL3, fval);
543 ret = menelaus_write_reg(MENELAUS_VCORE_CTRL4, rval);
550 ret = menelaus_write_reg(MENELAUS_VCORE_CTRL1, val);
737 ret = menelaus_write_reg(MENELAUS_SLEEP_CTRL2, val);
751 ret = menelaus_write_reg(MENELAUS_GPIO_CTRL, ret);
847 status = menelaus_write_reg(regnum++, bin2bcd(t->tm_sec));
851 status = menelaus_write_reg(regnum++, bin2bcd(t->tm_min));
863 status = menelaus_write_reg(regnum++, hour);
867 status = menelaus_write_reg(regnum++, bin2bcd(t->tm_mday));
871 status = menelaus_write_reg(regnum++, bin2bcd(t->tm_mon + 1));
875 status = menelaus_write_reg(regnum++, bin2bcd(t->tm_year - 100));
925 status = menelaus_write_reg(MENELAUS_RTC_WKDAY, bin2bcd(t->tm_wday));
933 status = menelaus_write_reg(MENELAUS_RTC_UPDATE, RTC_UPDATE_EVERY);
986 status = menelaus_write_reg(MENELAUS_RTC_CTRL,
1000 status = menelaus_write_reg(MENELAUS_RTC_CTRL,
1054 return menelaus_write_reg(MENELAUS_RTC_CTRL, the_menelaus->rtc_control);
1078 menelaus_write_reg(MENELAUS_RTC_CTRL, the_menelaus->rtc_control);
1119 menelaus_write_reg(MENELAUS_RTC_CTRL, m->rtc_control);
1176 menelaus_write_reg(MENELAUS_INT_ACK1, 0xff);
1177 menelaus_write_reg(MENELAUS_INT_ACK2, 0xff);
1178 menelaus_write_reg(MENELAUS_INT_MASK1, 0xff);
1179 menelaus_write_reg(MENELAUS_INT_MASK2, 0xff);
1184 menelaus_write_reg(MENELAUS_MCT_CTRL1, 0x73);