Lines Matching refs:val
560 u32 val;
564 val = readl(prcmu_base + reg);
565 val = ((val & ~mask) | (value & mask));
566 writel(val, (prcmu_base + reg));
591 * @val: Value to be set, i.e. transition requested
597 int prcmu_set_rc_a2p(enum romcode_write val)
599 if (val < RDY_2_DS || val > RDY_2_XP70_RST)
601 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
642 u32 val;
670 val = readl(PRCM_CLKOCR);
671 if (val & div_mask) {
673 if ((val & mask) != bits) {
678 if ((val & mask & ~div_mask) != bits) {
684 writel((bits | (val & ~mask)), PRCM_CLKOCR);
870 u32 val;
873 val = readl(prcmu_base + clock_reg[i]);
874 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
887 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
889 writel(val, prcmu_base + clock_reg[i]);
1223 u32 val;
1231 val = 0;
1233 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1236 val |= PRCM_TCR_STOP_TIMERS |
1240 writel(val, PRCM_TCR);
1247 u32 val;
1256 val = readl(prcmu_base + clk_mgt[clock].offset);
1258 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1260 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1261 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1263 writel(val, prcmu_base + clk_mgt[clock].offset);
1275 u32 val;
1279 val = readl(PRCM_CGATING_BYPASS);
1280 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1286 val = readl(PRCM_CGATING_BYPASS);
1287 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1305 u32 val;
1311 val = readl(PRCM_PLLDSI_ENABLE);
1313 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1315 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1316 writel(val, PRCM_PLLDSI_ENABLE);
1333 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1334 writel(val, PRCM_PLLDSI_ENABLE);
1345 u32 val;
1347 val = readl(PRCM_DSI_PLLOUT_SEL);
1348 val &= ~dsiclk[n].divsel_mask;
1349 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1351 writel(val, PRCM_DSI_PLLOUT_SEL);
1357 u32 val;
1359 val = readl(PRCM_DSITVCLK_DIV);
1360 enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1361 writel(val, PRCM_DSITVCLK_DIV);
1399 u32 val;
1403 val = readl(reg);
1406 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1408 d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1412 d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1416 if (val & PRCM_PLL_FREQ_SELDIV2)
1420 (val & PRCM_PLL_FREQ_DIV2EN) &&
1435 u32 val;
1439 val = readl(prcmu_base + clk_mgt[clock].offset);
1441 if (val & PRCM_CLK_MGT_CLK38) {
1442 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1447 val |= clk_mgt[clock].pllsw;
1448 pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1460 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1466 val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1467 if (val)
1468 return rate / val;
1595 u32 val;
1600 val = readl(prcmu_base + clk_mgt[clock].offset);
1601 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1604 if (val & PRCM_CLK_MGT_CLK38) {
1749 u32 val;
1760 val = readl(prcmu_base + clk_mgt[clock].offset);
1761 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1764 if (val & PRCM_CLK_MGT_CLK38) {
1767 val |= PRCM_CLK_MGT_CLK38DIV;
1769 val &= ~PRCM_CLK_MGT_CLK38DIV;
1772 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1779 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1783 val |= min(div, (u32)31);
1785 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1786 val |= min(div, (u32)31);
1788 writel(val, prcmu_base + clk_mgt[clock].offset);
1875 u32 val;
1885 val = readl(PRCM_DSI_PLLOUT_SEL);
1886 val &= ~dsiclk[n].divsel_mask;
1887 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1888 writel(val, PRCM_DSI_PLLOUT_SEL);
1893 u32 val;
1897 val = readl(PRCM_DSITVCLK_DIV);
1898 val &= ~dsiescclk[n].div_mask;
1899 val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1900 writel(val, PRCM_DSITVCLK_DIV);
1984 static int config_hot_period(u16 val)
1991 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2202 u32 val;
2207 val = readl(PRCM_HOSTACCESS_REQ);
2208 if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2218 val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2219 writel(val, PRCM_HOSTACCESS_REQ);
2223 val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2224 writel(val, PRCM_HOSTACCESS_REQ);
2243 u32 val;
2247 val = readl(PRCM_HOSTACCESS_REQ);
2248 if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2251 writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2699 u32 val;
2701 val = readl(PRCM_A9PL_FORCE_CLKEN);
2702 val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2704 writel(val, (PRCM_A9PL_FORCE_CLKEN));