Lines Matching refs:clk_mgt
452 struct clk_mgt {
469 static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
1256 val = readl(prcmu_base + clk_mgt[clock].offset);
1258 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1260 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1263 writel(val, prcmu_base + clk_mgt[clock].offset);
1439 val = readl(prcmu_base + clk_mgt[clock].offset);
1442 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1447 val |= clk_mgt[clock].pllsw;
1451 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1453 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1455 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1600 val = readl(prcmu_base + clk_mgt[clock].offset);
1601 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1602 clk_mgt[clock].branch);
1605 if (clk_mgt[clock].clk38div) {
1760 val = readl(prcmu_base + clk_mgt[clock].offset);
1761 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1762 clk_mgt[clock].branch);
1765 if (clk_mgt[clock].clk38div) {
1788 writel(val, prcmu_base + clk_mgt[clock].offset);