Lines Matching defs:rate
1398 u64 rate;
1405 rate = src_rate;
1406 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1426 (void)do_div(rate, div);
1428 return (unsigned long)rate;
1437 unsigned long rate = ROOT_CLOCK_RATE;
1443 rate /= 2;
1444 return rate;
1451 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1453 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1455 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1461 u64 r = (rate * 10);
1468 return rate / val;
1476 unsigned long rate;
1483 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1487 rate /= 2;
1492 rate /= r;
1495 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1498 return rate;
1581 static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1585 div = (src_rate / rate);
1588 if (rate < (src_rate / div))
1593 static long round_clock_rate(u8 clock, unsigned long rate)
1603 div = clock_divider(src_rate, rate);
1615 if (r <= rate)
1638 static long round_armss_rate(unsigned long rate)
1656 if (rate <= freq)
1667 static long round_plldsi_rate(unsigned long rate)
1675 rem = rate;
1680 d = (r * rate);
1691 if (rate < d) {
1696 if ((rate - d) < rem) {
1697 rem = (rate - d);
1704 static long round_dsiclk_rate(unsigned long rate)
1712 div = clock_divider(src_rate, rate);
1718 static long round_dsiescclk_rate(unsigned long rate)
1725 div = clock_divider(src_rate, rate);
1731 long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1734 return round_clock_rate(clock, rate);
1736 return round_armss_rate(rate);
1738 return round_plldsi_rate(rate);
1740 return round_dsiclk_rate(rate);
1742 return round_dsiescclk_rate(rate);
1747 static void set_clock_rate(u8 clock, unsigned long rate)
1763 div = clock_divider(src_rate, rate);
1778 if (r <= rate) {
1796 static int set_armss_rate(unsigned long rate)
1815 if (rate == freq)
1819 if (rate != freq)
1827 static int set_plldsi_rate(unsigned long rate)
1835 rem = rate;
1841 d = (r * rate);
1852 if (rate < hwrate) {
1858 if ((rate - hwrate) < rem) {
1859 rem = (rate - hwrate);
1873 static void set_dsiclk_rate(u8 n, unsigned long rate)
1879 clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1891 static void set_dsiescclk_rate(u8 n, unsigned long rate)
1896 div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1903 int prcmu_set_clock_rate(u8 clock, unsigned long rate)
1906 set_clock_rate(clock, rate);
1908 return set_armss_rate(rate);
1910 return set_plldsi_rate(rate);
1912 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
1914 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);