Lines Matching refs:shift
82 * @shift: the position of the Txx field in the TIMINGS register
88 * @conf->timings field at @shift position.
90 * Returns -EINVAL if shift is invalid, -ERANGE if ncycles does not fit in
94 unsigned int shift, unsigned int ncycles)
99 if (shift != ATMEL_HSMC_TIMINGS_TCLR_SHIFT &&
100 shift != ATMEL_HSMC_TIMINGS_TADL_SHIFT &&
101 shift != ATMEL_HSMC_TIMINGS_TAR_SHIFT &&
102 shift != ATMEL_HSMC_TIMINGS_TRR_SHIFT &&
103 shift != ATMEL_HSMC_TIMINGS_TWB_SHIFT)
113 conf->timings &= ~GENMASK(shift + 3, shift);
114 conf->timings |= val << shift;
124 * @shift: the position of the xx_SETUP field in the SETUP register
130 * @conf->setup field at @shift position.
132 * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
136 unsigned int shift, unsigned int ncycles)
141 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&
142 shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)
152 conf->setup &= ~GENMASK(shift + 7, shift);
153 conf->setup |= val << shift;
163 * @shift: the position of the xx_PULSE field in the PULSE register
169 * @conf->setup field at @shift position.
171 * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
175 unsigned int shift, unsigned int ncycles)
180 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&
181 shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)
191 conf->pulse &= ~GENMASK(shift + 7, shift);
192 conf->pulse |= val << shift;
202 * @shift: the position of the xx_CYCLE field in the CYCLE register
208 * @conf->setup field at @shift position.
210 * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
214 unsigned int shift, unsigned int ncycles)
219 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NRD_SHIFT)
229 conf->cycle &= ~GENMASK(shift + 15, shift);
230 conf->cycle |= val << shift;