Lines Matching refs:addr
49 void __iomem *addr;
169 while (!(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) {
172 *(unsigned int *)(buf + off) = __raw_readl(host->addr + DATA);
178 && !(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) {
179 host->io_word[0] = readl(host->addr + DATA);
233 && !(STATUS_FIFO_FULL & readl(host->addr + STATUS))) {
234 writel(host->io_word[0], host->addr + DATA);
244 while (!(STATUS_FIFO_FULL & readl(host->addr + STATUS))) {
249 host->addr + DATA);
356 writel(host->io_word[0], host->addr + TPC_P0);
357 writel(host->io_word[1], host->addr + TPC_P1);
359 writel(host->io_word[0], host->addr + DATA);
371 if (!(STATUS_HAS_MEDIA & readl(host->addr + STATUS))) {
377 dev_dbg(&msh->dev, "control %08x\n", readl(host->addr + HOST_CONTROL));
378 dev_dbg(&msh->dev, "status %08x\n", readl(host->addr + INT_STATUS));
379 dev_dbg(&msh->dev, "hstatus %08x\n", readl(host->addr + STATUS));
427 host->addr + DMA_ADDRESS);
430 host->addr + BLOCK);
431 writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL);
435 host->addr + BLOCK);
436 t_val = readl(host->addr + INT_STATUS_ENABLE);
441 writel(t_val, host->addr + INT_STATUS_ENABLE);
442 writel(t_val, host->addr + INT_SIGNAL_ENABLE);
450 writel(host->io_word[0], host->addr + TPC_P0);
451 writel(host->io_word[1], host->addr + TPC_P1);
456 writel(HOST_CONTROL_LED | readl(host->addr + HOST_CONTROL),
457 host->addr + HOST_CONTROL);
460 writel(cmd, host->addr + TPC);
475 readl(host->addr + HOST_CONTROL));
477 readl(host->addr + INT_STATUS));
478 dev_dbg(&msh->dev, "c hstatus %08x\n", readl(host->addr + STATUS));
480 host->req->int_reg = readl(host->addr + STATUS) & 0xff;
482 writel(0, host->addr + BLOCK);
483 writel(0, host->addr + DMA_CONTROL);
490 t_val = readl(host->addr + INT_STATUS_ENABLE);
496 writel(t_val, host->addr + INT_STATUS_ENABLE);
497 writel(t_val, host->addr + INT_SIGNAL_ENABLE);
500 writel((~HOST_CONTROL_LED) & readl(host->addr + HOST_CONTROL),
501 host->addr + HOST_CONTROL);
523 irq_status = readl(host->addr + INT_STATUS);
559 = readl(host->addr
562 = readl(host->addr
579 writel(irq_status, host->addr + INT_STATUS);
640 | readl(host->addr + HOST_CONTROL),
641 host->addr + HOST_CONTROL);
645 & readl(host->addr + HOST_CONTROL)))
654 | readl(host->addr + HOST_CONTROL),
655 host->addr + HOST_CONTROL);
659 & readl(host->addr + HOST_CONTROL)))
668 writel(INT_STATUS_ALL, host->addr + INT_SIGNAL_ENABLE);
669 writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE);
678 unsigned int host_ctl = readl(host->addr + HOST_CONTROL);
692 writel(host_ctl, host->addr + HOST_CONTROL);
696 host->addr + PAD_PU_PD);
699 host->addr + PAD_OUTPUT_ENABLE);
706 writel(host_ctl, host->addr + HOST_CONTROL);
707 writel(0, host->addr + PAD_OUTPUT_ENABLE);
708 writel(PAD_PU_PD_OFF, host->addr + PAD_PU_PD);
743 writel(host_ctl, host->addr + HOST_CONTROL);
744 writel(CLOCK_CONTROL_OFF, host->addr + CLOCK_CONTROL);
745 writel(clock_ctl, host->addr + CLOCK_CONTROL);
859 host->addr = ioremap(pci_resource_start(jm->pdev, cnt),
861 if (!host->addr)
883 iounmap(host->addr);
894 iounmap(host->addr);
984 writel(0, host->addr + INT_SIGNAL_ENABLE);
985 writel(0, host->addr + INT_STATUS_ENABLE);