Lines Matching defs:timing
409 dev_err(emc->dev, "failed to update timing: %d\n", err);
440 struct emc_timing *timing = NULL;
445 timing = &emc->timings[i];
450 if (!timing) {
451 dev_err(emc->dev, "no timing for rate %lu\n", rate);
455 return timing;
458 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing,
464 if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) {
475 if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) {
486 if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) {
525 struct emc_timing *timing = emc_find_timing(emc, rate);
538 if (!timing || emc->bad_state)
541 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
542 __func__, timing->rate, rate);
557 if (emc->dll_on == !!(timing->emc_mode_1 & 0x1))
559 else if (timing->emc_mode_1 & 0x1)
564 emc->dll_on = !!(timing->emc_mode_1 & 0x1);
566 if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL))
601 if (emc_dqs_preset(emc, timing, &schmitt_to_vref)) {
615 if (timing->emc_auto_cal_interval) {
617 val ^= timing->data[74];
636 for (i = 0; i < ARRAY_SIZE(timing->data); i++) {
639 writel_relaxed(timing->data[i],
643 err = tegra_mc_write_emem_configuration(emc->mc, timing->rate);
654 val = timing->data[82] & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK;
658 val = timing->data[82] & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
674 new_mode = timing->data[39] & EMC_CFG5_QUSE_MODE_MASK;
703 writel_relaxed(timing->emc_mode_1,
716 writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL);
720 if (qrst_used || timing->emc_cfg_periodic_qrst != val) {
721 if (timing->emc_cfg_periodic_qrst)
737 if (timing->emc_mode_1 != emc->emc_mode_1)
738 writel_relaxed(timing->emc_mode_1,
741 if (timing->emc_mode_2 != emc->emc_mode_2)
742 writel_relaxed(timing->emc_mode_2,
745 if (timing->emc_mode_reset != emc->emc_mode_reset ||
747 val = timing->emc_mode_reset;
757 if (timing->emc_mode_2 != emc->emc_mode_2)
758 writel_relaxed(timing->emc_mode_2,
761 if (timing->emc_mode_1 != emc->emc_mode_1)
762 writel_relaxed(timing->emc_mode_1,
766 emc->emc_mode_1 = timing->emc_mode_1;
767 emc->emc_mode_2 = timing->emc_mode_2;
768 emc->emc_mode_reset = timing->emc_mode_reset;
795 struct emc_timing *timing = emc_find_timing(emc, rate);
815 writel_relaxed(timing->emc_auto_cal_interval,
819 if (timing->emc_cfg_dyn_self_ref) {
826 writel_relaxed(timing->emc_zcal_cnt_long,
832 /* update restored timing */
848 dev_err(emc->dev, "timing configuration can't be reverted\n");
889 struct emc_timing *timing,
897 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
902 timing->rate = value;
905 timing->data,
909 "timing %pOF: failed to read emc timing data: %d\n",
915 timing->prop = of_property_read_bool(node, dtprop);
918 err = of_property_read_u32(node, dtprop, &timing->prop); \
921 "timing %pOFn: failed to read " #prop ": %d\n", \
937 dev_dbg(emc->dev, "%s: %pOF: rate %lu\n", __func__, node, timing->rate);
970 "emc/mc timing rate mismatch: %lu %lu\n",
983 struct emc_timing *timing;
993 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
999 timing = emc->timings;
1002 err = load_one_timing_from_dt(emc, timing++, child);
1009 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
1198 struct emc_timing *timing = NULL;
1221 timing = &emc->timings[i];
1225 if (!timing) {
1226 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
1231 return timing->rate;