Lines Matching defs:emc
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
398 static int emc_seq_update_timing(struct tegra_emc *emc)
403 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL);
405 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val,
409 dev_err(emc->dev, "failed to update timing: %d\n", err);
418 struct tegra_emc *emc = data;
422 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
428 dev_err_ratelimited(emc->dev,
432 writel_relaxed(status, emc->regs + EMC_INTSTATUS);
437 static struct emc_timing *emc_find_timing(struct tegra_emc *emc,
443 for (i = 0; i < emc->num_timings; i++) {
444 if (emc->timings[i].rate >= rate) {
445 timing = &emc->timings[i];
451 dev_err(emc->dev, "no timing for rate %lu\n", rate);
458 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing,
465 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL2);
469 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2);
476 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL3);
480 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL3);
487 val = readl_relaxed(emc->regs + EMC_XM2QUSEPADCTRL);
491 writel_relaxed(val, emc->regs + EMC_XM2QUSEPADCTRL);
501 static int emc_prepare_mc_clk_cfg(struct tegra_emc *emc, unsigned long rate)
503 struct tegra_mc *mc = emc->mc;
517 return tegra20_clk_prepare_emc_mc_same_freq(emc->clk, same);
523 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
525 struct emc_timing *timing = emc_find_timing(emc, rate);
538 if (!timing || emc->bad_state)
541 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
544 emc->bad_state = true;
546 err = emc_prepare_mc_clk_cfg(emc, rate);
548 dev_err(emc->dev, "mc clock preparation failed: %d\n", err);
552 emc->vref_cal_toggle = false;
553 emc->mc_override = mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);
554 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG);
555 emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
557 if (emc->dll_on == !!(timing->emc_mode_1 & 0x1))
564 emc->dll_on = !!(timing->emc_mode_1 & 0x1);
566 if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL))
567 emc->zcal_long = true;
569 emc->zcal_long = false;
571 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
574 dram_num = tegra_mc_get_emem_device_count(emc->mc);
577 if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) {
578 emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE;
579 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
585 val = mc_readl(emc->mc, MC_EMEM_ARB_OUTSTANDING_REQ);
591 mc_writel(emc->mc, val, MC_EMEM_ARB_OUTSTANDING_REQ);
592 mc_writel(emc->mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
595 if (emc->mc_override & MC_EMEM_ARB_OVERRIDE_EACK_MASK)
596 mc_writel(emc->mc,
597 emc->mc_override & ~MC_EMEM_ARB_OVERRIDE_EACK_MASK,
601 if (emc_dqs_preset(emc, timing, &schmitt_to_vref)) {
607 err = emc_seq_update_timing(emc);
616 val = readl_relaxed(emc->regs + EMC_XM2COMPPADCTRL);
620 writel_relaxed(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
623 emc->regs + EMC_AUTO_CAL_STATUS, val,
626 dev_err(emc->dev,
631 emc->vref_cal_toggle = true;
640 emc->regs + emc_timing_registers[i]);
643 err = tegra_mc_write_emem_configuration(emc->mc, timing->rate);
651 if (emc->zcal_long)
662 writel_relaxed(val, emc->regs + EMC_MRS_WAIT_CNT);
666 val = readl_relaxed(emc->regs + EMC_SEL_DPD_CTRL);
685 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE);
690 emc->regs + EMC_DBG);
691 writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST,
692 emc->regs + EMC_CFG);
693 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
698 emc->regs + EMC_REFCTRL);
704 emc->regs + EMC_EMRS);
708 emc->regs + EMC_SELF_REF);
712 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
715 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG);
716 writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL);
719 val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST);
722 emc->emc_cfg |= EMC_CFG_PERIODIC_QRST;
724 emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST;
726 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
728 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
733 emc->regs + EMC_SELF_REF);
737 if (timing->emc_mode_1 != emc->emc_mode_1)
739 emc->regs + EMC_EMRS);
741 if (timing->emc_mode_2 != emc->emc_mode_2)
743 emc->regs + EMC_EMRS);
745 if (timing->emc_mode_reset != emc->emc_mode_reset ||
754 writel_relaxed(val, emc->regs + EMC_MRS);
757 if (timing->emc_mode_2 != emc->emc_mode_2)
759 emc->regs + EMC_MRW);
761 if (timing->emc_mode_1 != emc->emc_mode_1)
763 emc->regs + EMC_MRW);
766 emc->emc_mode_1 = timing->emc_mode_1;
767 emc->emc_mode_2 = timing->emc_mode_2;
768 emc->emc_mode_reset = timing->emc_mode_reset;
771 if (emc->zcal_long) {
773 emc->regs + EMC_ZQ_CAL);
777 emc->regs + EMC_ZQ_CAL);
781 writel_relaxed(0x1, emc->regs + EMC_UNSTALL_RW_AFTER_CLKCHANGE);
787 mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);
792 static int emc_complete_timing_change(struct tegra_emc *emc,
795 struct emc_timing *timing = emc_find_timing(emc, rate);
800 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
804 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err);
809 dram_num = tegra_mc_get_emem_device_count(emc->mc);
811 emc->regs + EMC_REFCTRL);
814 if (emc->vref_cal_toggle)
816 emc->regs + EMC_AUTO_CAL_INTERVAL);
820 emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE;
821 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
825 if (emc->zcal_long)
827 emc->regs + EMC_ZCAL_WAIT_CNT);
833 err = emc_seq_update_timing(emc);
835 emc->bad_state = false;
838 mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE);
843 static int emc_unprepare_timing_change(struct tegra_emc *emc,
846 if (!emc->bad_state) {
848 dev_err(emc->dev, "timing configuration can't be reverted\n");
849 emc->bad_state = true;
858 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
868 disable_irq(emc->irq);
869 err = emc_prepare_timing_change(emc, cnd->new_rate);
870 enable_irq(emc->irq);
874 err = emc_unprepare_timing_change(emc, cnd->old_rate);
878 err = emc_complete_timing_change(emc, cnd->new_rate);
888 static int load_one_timing_from_dt(struct tegra_emc *emc,
897 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
904 err = of_property_read_u32_array(node, "nvidia,emc-configuration",
908 dev_err(emc->dev,
909 "timing %pOF: failed to read emc timing data: %d\n",
920 dev_err(emc->dev, \
926 EMC_READ_U32(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
927 EMC_READ_U32(emc_mode_1, "nvidia,emc-mode-1")
928 EMC_READ_U32(emc_mode_2, "nvidia,emc-mode-2")
929 EMC_READ_U32(emc_mode_reset, "nvidia,emc-mode-reset")
930 EMC_READ_U32(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
931 EMC_READ_BOOL(emc_cfg_dyn_self_ref, "nvidia,emc-cfg-dyn-self-ref")
932 EMC_READ_BOOL(emc_cfg_periodic_qrst, "nvidia,emc-cfg-periodic-qrst")
937 dev_dbg(emc->dev, "%s: %pOF: rate %lu\n", __func__, node, timing->rate);
956 static int emc_check_mc_timings(struct tegra_emc *emc)
958 struct tegra_mc *mc = emc->mc;
961 if (emc->num_timings != mc->num_timings) {
962 dev_err(emc->dev, "emc/mc timings number mismatch: %u %u\n",
963 emc->num_timings, mc->num_timings);
968 if (emc->timings[i].rate != mc->timings[i].rate) {
969 dev_err(emc->dev,
970 "emc/mc timing rate mismatch: %lu %lu\n",
971 emc->timings[i].rate, mc->timings[i].rate);
979 static int emc_load_timings_from_dt(struct tegra_emc *emc,
989 dev_err(emc->dev, "no memory timings in: %pOF\n", node);
993 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
995 if (!emc->timings)
998 emc->num_timings = child_count;
999 timing = emc->timings;
1002 err = load_one_timing_from_dt(emc, timing++, child);
1009 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
1012 err = emc_check_mc_timings(emc);
1016 dev_info_once(emc->dev,
1018 emc->num_timings,
1020 emc->timings[0].rate / 1000000,
1021 emc->timings[emc->num_timings - 1].rate / 1000000);
1026 static struct device_node *emc_find_node_by_ram_code(struct tegra_emc *emc)
1028 struct device *dev = emc->dev;
1033 if (emc->mrr_error) {
1059 static int emc_read_lpddr_mode_register(struct tegra_emc *emc,
1069 writel_relaxed(EMC_MRR_DIVLD_INT, emc->regs + EMC_INTSTATUS);
1075 writel_relaxed(val, emc->regs + EMC_MRR);
1078 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, val,
1082 dev_err(emc->dev, "mode register %u read failed: %d\n",
1084 emc->mrr_error = true;
1089 val = readl_relaxed(emc->regs + EMC_MRR);
1095 static void emc_read_lpddr_sdram_info(struct tegra_emc *emc,
1104 emc_read_lpddr_mode_register(emc, emem_dev, 5, &manufacturer_id);
1105 emc_read_lpddr_mode_register(emc, emem_dev, 6, &revision_id1);
1106 emc_read_lpddr_mode_register(emc, emem_dev, 7, &revision_id2);
1107 emc_read_lpddr_mode_register(emc, emem_dev, 8, &basic_conf4.value);
1109 dev_info(emc->dev, "SDRAM[dev%u]: manufacturer: 0x%x (%s) rev1: 0x%x rev2: 0x%x prefetch: S%u density: %uMbit iowidth: %ubit\n",
1118 static int emc_setup_hw(struct tegra_emc *emc)
1127 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
1130 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
1148 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
1151 writel_relaxed(intmask, emc->regs + EMC_INTMASK);
1152 writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS);
1155 emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
1160 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
1177 emc_adr_cfg = readl_relaxed(emc->regs + EMC_ADR_CFG);
1180 dev_info_once(emc->dev, "%u %s %s attached\n", emem_numdev,
1185 emc_read_lpddr_sdram_info(emc, emem_numdev);
1199 struct tegra_emc *emc = arg;
1202 if (!emc->num_timings)
1203 return clk_get_rate(emc->clk);
1205 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
1207 for (i = 0; i < emc->num_timings; i++) {
1208 if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
1211 if (emc->timings[i].rate > max_rate) {
1214 if (emc->timings[i].rate < min_rate)
1218 if (emc->timings[i].rate < min_rate)
1221 timing = &emc->timings[i];
1226 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
1234 static void tegra_emc_rate_requests_init(struct tegra_emc *emc)
1239 emc->requested_rate[i].min_rate = 0;
1240 emc->requested_rate[i].max_rate = ULONG_MAX;
1244 static int emc_request_rate(struct tegra_emc *emc,
1249 struct emc_rate_request *req = emc->requested_rate;
1266 dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
1275 err = dev_pm_opp_set_rate(emc->dev, min_rate);
1279 emc->requested_rate[type].min_rate = new_min_rate;
1280 emc->requested_rate[type].max_rate = new_max_rate;
1285 static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
1288 struct emc_rate_request *req = &emc->requested_rate[type];
1291 mutex_lock(&emc->rate_lock);
1292 ret = emc_request_rate(emc, rate, req->max_rate, type);
1293 mutex_unlock(&emc->rate_lock);
1298 static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
1301 struct emc_rate_request *req = &emc->requested_rate[type];
1304 mutex_lock(&emc->rate_lock);
1305 ret = emc_request_rate(emc, req->min_rate, rate, type);
1306 mutex_unlock(&emc->rate_lock);
1317 * /sys/kernel/debug/emc
1336 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
1340 for (i = 0; i < emc->num_timings; i++)
1341 if (rate == emc->timings[i].rate)
1349 struct tegra_emc *emc = s->private;
1353 for (i = 0; i < emc->num_timings; i++) {
1354 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
1366 struct tegra_emc *emc = data;
1368 *rate = emc->debugfs.min_rate;
1375 struct tegra_emc *emc = data;
1378 if (!tegra_emc_validate_rate(emc, rate))
1381 err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
1385 emc->debugfs.min_rate = rate;
1396 struct tegra_emc *emc = data;
1398 *rate = emc->debugfs.max_rate;
1405 struct tegra_emc *emc = data;
1408 if (!tegra_emc_validate_rate(emc, rate))
1411 err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
1415 emc->debugfs.max_rate = rate;
1424 static void tegra_emc_debugfs_init(struct tegra_emc *emc)
1426 struct device *dev = emc->dev;
1430 emc->debugfs.min_rate = ULONG_MAX;
1431 emc->debugfs.max_rate = 0;
1433 for (i = 0; i < emc->num_timings; i++) {
1434 if (emc->timings[i].rate < emc->debugfs.min_rate)
1435 emc->debugfs.min_rate = emc->timings[i].rate;
1437 if (emc->timings[i].rate > emc->debugfs.max_rate)
1438 emc->debugfs.max_rate = emc->timings[i].rate;
1441 if (!emc->num_timings) {
1442 emc->debugfs.min_rate = clk_get_rate(emc->clk);
1443 emc->debugfs.max_rate = emc->debugfs.min_rate;
1446 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
1447 emc->debugfs.max_rate);
1450 emc->debugfs.min_rate, emc->debugfs.max_rate,
1451 emc->clk);
1454 emc->debugfs.root = debugfs_create_dir("emc", NULL);
1456 debugfs_create_file("available_rates", 0444, emc->debugfs.root,
1457 emc, &tegra_emc_debug_available_rates_fops);
1458 debugfs_create_file("min_rate", 0644, emc->debugfs.root,
1459 emc, &tegra_emc_debug_min_rate_fops);
1460 debugfs_create_file("max_rate", 0644, emc->debugfs.root,
1461 emc, &tegra_emc_debug_max_rate_fops);
1501 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
1517 err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
1524 static int tegra_emc_interconnect_init(struct tegra_emc *emc)
1526 const struct tegra_mc_soc *soc = emc->mc->soc;
1530 emc->provider.dev = emc->dev;
1531 emc->provider.set = emc_icc_set;
1532 emc->provider.data = &emc->provider;
1533 emc->provider.aggregate = soc->icc_ops->aggregate;
1534 emc->provider.xlate_extended = emc_of_icc_xlate_extended;
1536 icc_provider_init(&emc->provider);
1546 icc_node_add(node, &emc->provider);
1561 icc_node_add(node, &emc->provider);
1563 err = icc_provider_register(&emc->provider);
1570 icc_nodes_remove(&emc->provider);
1572 dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
1584 struct tegra_emc *emc = data;
1586 clk_notifier_unregister(emc->clk, &emc->clk_nb);
1589 static int tegra_emc_init_clk(struct tegra_emc *emc)
1593 tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
1595 err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback,
1600 emc->clk = devm_clk_get(emc->dev, NULL);
1601 if (IS_ERR(emc->clk)) {
1602 dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk);
1603 return PTR_ERR(emc->clk);
1606 err = clk_notifier_register(emc->clk, &emc->clk_nb);
1608 dev_err(emc->dev, "failed to register clk notifier: %d\n", err);
1612 err = devm_add_action_or_reset(emc->dev,
1613 devm_tegra_emc_unreg_clk_notifier, emc);
1624 struct tegra_emc *emc;
1627 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1628 if (!emc)
1631 emc->mc = devm_tegra_memory_controller_get(&pdev->dev);
1632 if (IS_ERR(emc->mc))
1633 return PTR_ERR(emc->mc);
1635 mutex_init(&emc->rate_lock);
1636 emc->clk_nb.notifier_call = emc_clk_change_notify;
1637 emc->dev = &pdev->dev;
1639 emc->regs = devm_platform_ioremap_resource(pdev, 0);
1640 if (IS_ERR(emc->regs))
1641 return PTR_ERR(emc->regs);
1643 err = emc_setup_hw(emc);
1647 np = emc_find_node_by_ram_code(emc);
1649 err = emc_load_timings_from_dt(emc, np);
1659 emc->irq = err;
1661 err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0,
1662 dev_name(&pdev->dev), emc);
1668 err = tegra_emc_init_clk(emc);
1678 platform_set_drvdata(pdev, emc);
1679 tegra_emc_rate_requests_init(emc);
1680 tegra_emc_debugfs_init(emc);
1681 tegra_emc_interconnect_init(emc);
1695 struct tegra_emc *emc = dev_get_drvdata(dev);
1699 err = clk_rate_exclusive_get(emc->clk);
1701 dev_err(emc->dev, "failed to acquire clk: %d\n", err);
1706 if (WARN(emc->bad_state, "hardware in a bad state\n"))
1709 emc->bad_state = true;
1716 struct tegra_emc *emc = dev_get_drvdata(dev);
1718 emc_setup_hw(emc);
1719 emc->bad_state = false;
1721 clk_rate_exclusive_put(emc->clk);
1732 { .compatible = "nvidia,tegra30-emc", },
1740 .name = "tegra30-emc",