Lines Matching refs:dram_timings
604 * However, we need it for accessing the dram_timings (which are not
612 u32 tFC_lpddr4 = 1000 * next->dram_timings[T_FC_LPDDR4];
925 tRTM = fake->dram_timings[RL] + div_o3(3600, src_clk_period) +
1313 value = (1000 * fake->dram_timings[T_RP]) / src_clk_period;
1322 delay += (1000 * fake->dram_timings[T_RP]) /
1324 delay += 4000 * fake->dram_timings[T_RFC];
1346 delay = ((1000 * fake->dram_timings[T_RP] / src_clk_period) +
1347 (1000 * fake->dram_timings[T_RFC] / src_clk_period));
1415 div_o3(1000 * next->dram_timings[T_PDEX],
1422 emc_dbg(emc, INFO, "next->dram_timings[T_PDEX] = %u\n",
1423 next->dram_timings[T_PDEX]);
1428 delay = div_o3(1000 * next->dram_timings[T_PDEX],