Lines Matching defs:emc
237 struct tegra_emc *emc = data;
241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
247 dev_err_ratelimited(emc->dev,
251 writel_relaxed(status, emc->regs + EMC_INTSTATUS);
256 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
262 for (i = 0; i < emc->num_timings; i++) {
263 if (emc->timings[i].rate >= rate) {
264 timing = &emc->timings[i];
270 dev_err(emc->dev, "no timing for rate %lu\n", rate);
277 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
279 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
285 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
291 emc->regs + emc_timing_registers[i]);
294 readl_relaxed(emc->regs + emc_timing_registers[i - 1]);
299 static int emc_complete_timing_change(struct tegra_emc *emc, bool flush)
304 dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush);
309 emc->regs + EMC_TIMING_CONTROL);
313 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
317 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err);
327 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
333 err = emc_prepare_timing_change(emc, cnd->new_rate);
337 err = emc_prepare_timing_change(emc, cnd->old_rate);
341 err = emc_complete_timing_change(emc, true);
345 err = emc_complete_timing_change(emc, false);
355 static int load_one_timing_from_dt(struct tegra_emc *emc,
362 if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) {
363 dev_err(emc->dev, "incompatible DT node: %pOF\n", node);
369 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
374 err = of_property_read_u32_array(node, "nvidia,emc-registers",
378 dev_err(emc->dev,
379 "timing %pOF: failed to read emc timing data: %d\n",
390 dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n",
410 static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
420 dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node);
424 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
426 if (!emc->timings)
429 timing = emc->timings;
435 err = load_one_timing_from_dt(emc, timing++, child);
441 emc->num_timings++;
444 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
447 dev_info_once(emc->dev,
449 emc->num_timings,
451 emc->timings[0].rate / 1000000,
452 emc->timings[emc->num_timings - 1].rate / 1000000);
458 tegra_emc_find_node_by_ram_code(struct tegra_emc *emc)
460 struct device *dev = emc->dev;
465 if (emc->mrr_error) {
480 for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np;
481 np = of_find_node_by_name(np, "emc-tables")) {
494 info->manufacturer_id != emc->manufacturer_id)
498 info->revision_id1 != emc->revision_id1)
502 info->revision_id2 != emc->revision_id2)
505 if (info->density != emc->basic_conf4.density)
508 if (info->io_width != emc->basic_conf4.io_width)
511 if (info->arch_type != emc->basic_conf4.arch_type)
538 static int emc_read_lpddr_mode_register(struct tegra_emc *emc,
548 writel_relaxed(EMC_MRR_DIVLD_INT, emc->regs + EMC_INTSTATUS);
554 writel_relaxed(val, emc->regs + EMC_MRR);
557 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, val,
561 dev_err(emc->dev, "mode register %u read failed: %d\n",
563 emc->mrr_error = true;
568 val = readl_relaxed(emc->regs + EMC_MRR);
574 static void emc_read_lpddr_sdram_info(struct tegra_emc *emc,
579 emc_read_lpddr_mode_register(emc, emem_dev, 5, &emc->manufacturer_id);
580 emc_read_lpddr_mode_register(emc, emem_dev, 6, &emc->revision_id1);
581 emc_read_lpddr_mode_register(emc, emem_dev, 7, &emc->revision_id2);
582 emc_read_lpddr_mode_register(emc, emem_dev, 8, &emc->basic_conf4.value);
587 dev_info(emc->dev, "SDRAM[dev%u]: manufacturer: 0x%x (%s) rev1: 0x%x rev2: 0x%x prefetch: S%u density: %uMbit iowidth: %ubit\n",
588 emem_dev, emc->manufacturer_id,
589 lpddr2_jedec_manufacturer(emc->manufacturer_id),
590 emc->revision_id1, emc->revision_id2,
591 4 >> emc->basic_conf4.arch_type,
592 64 << emc->basic_conf4.density,
593 32 >> emc->basic_conf4.io_width);
596 static int emc_setup_hw(struct tegra_emc *emc)
605 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
613 dev_err(emc->dev,
620 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
623 writel_relaxed(intmask, emc->regs + EMC_INTMASK);
624 writel_relaxed(intmask, emc->regs + EMC_INTSTATUS);
627 emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
632 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
634 emc_fbio = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
637 emc->dram_bus_width = 16;
639 emc->dram_bus_width = 32;
658 emc_adr_cfg = readl_relaxed(emc->regs + EMC_ADR_CFG_0);
661 dev_info_once(emc->dev, "%ubit DRAM bus, %u %s %s attached\n",
662 emc->dram_bus_width, emem_numdev, dram_type_str,
667 emc_read_lpddr_sdram_info(emc, emem_numdev,
681 struct tegra_emc *emc = arg;
684 if (!emc->num_timings)
685 return clk_get_rate(emc->clk);
687 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
689 for (i = 0; i < emc->num_timings; i++) {
690 if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
693 if (emc->timings[i].rate > max_rate) {
696 if (emc->timings[i].rate < min_rate)
700 if (emc->timings[i].rate < min_rate)
703 timing = &emc->timings[i];
708 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
716 static void tegra_emc_rate_requests_init(struct tegra_emc *emc)
721 emc->requested_rate[i].min_rate = 0;
722 emc->requested_rate[i].max_rate = ULONG_MAX;
726 static int emc_request_rate(struct tegra_emc *emc,
731 struct emc_rate_request *req = emc->requested_rate;
748 dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
757 err = dev_pm_opp_set_rate(emc->dev, min_rate);
761 emc->requested_rate[type].min_rate = new_min_rate;
762 emc->requested_rate[type].max_rate = new_max_rate;
767 static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
770 struct emc_rate_request *req = &emc->requested_rate[type];
773 mutex_lock(&emc->rate_lock);
774 ret = emc_request_rate(emc, rate, req->max_rate, type);
775 mutex_unlock(&emc->rate_lock);
780 static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
783 struct emc_rate_request *req = &emc->requested_rate[type];
786 mutex_lock(&emc->rate_lock);
787 ret = emc_request_rate(emc, req->min_rate, rate, type);
788 mutex_unlock(&emc->rate_lock);
799 * /sys/kernel/debug/emc
818 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
822 for (i = 0; i < emc->num_timings; i++)
823 if (rate == emc->timings[i].rate)
831 struct tegra_emc *emc = s->private;
835 for (i = 0; i < emc->num_timings; i++) {
836 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
848 struct tegra_emc *emc = data;
850 *rate = emc->debugfs.min_rate;
857 struct tegra_emc *emc = data;
860 if (!tegra_emc_validate_rate(emc, rate))
863 err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
867 emc->debugfs.min_rate = rate;
878 struct tegra_emc *emc = data;
880 *rate = emc->debugfs.max_rate;
887 struct tegra_emc *emc = data;
890 if (!tegra_emc_validate_rate(emc, rate))
893 err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
897 emc->debugfs.max_rate = rate;
906 static void tegra_emc_debugfs_init(struct tegra_emc *emc)
908 struct device *dev = emc->dev;
912 emc->debugfs.min_rate = ULONG_MAX;
913 emc->debugfs.max_rate = 0;
915 for (i = 0; i < emc->num_timings; i++) {
916 if (emc->timings[i].rate < emc->debugfs.min_rate)
917 emc->debugfs.min_rate = emc->timings[i].rate;
919 if (emc->timings[i].rate > emc->debugfs.max_rate)
920 emc->debugfs.max_rate = emc->timings[i].rate;
923 if (!emc->num_timings) {
924 emc->debugfs.min_rate = clk_get_rate(emc->clk);
925 emc->debugfs.max_rate = emc->debugfs.min_rate;
928 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
929 emc->debugfs.max_rate);
932 emc->debugfs.min_rate, emc->debugfs.max_rate,
933 emc->clk);
936 emc->debugfs.root = debugfs_create_dir("emc", NULL);
938 debugfs_create_file("available_rates", 0444, emc->debugfs.root,
939 emc, &tegra_emc_debug_available_rates_fops);
940 debugfs_create_file("min_rate", 0644, emc->debugfs.root,
941 emc, &tegra_emc_debug_min_rate_fops);
942 debugfs_create_file("max_rate", 0644, emc->debugfs.root,
943 emc, &tegra_emc_debug_max_rate_fops);
983 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
995 dram_data_bus_width_bytes = emc->dram_bus_width / 8;
999 err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
1006 static int tegra_emc_interconnect_init(struct tegra_emc *emc)
1012 emc->mc = devm_tegra_memory_controller_get(emc->dev);
1013 if (IS_ERR(emc->mc))
1014 return PTR_ERR(emc->mc);
1016 soc = emc->mc->soc;
1018 emc->provider.dev = emc->dev;
1019 emc->provider.set = emc_icc_set;
1020 emc->provider.data = &emc->provider;
1021 emc->provider.aggregate = soc->icc_ops->aggregate;
1022 emc->provider.xlate_extended = emc_of_icc_xlate_extended;
1024 icc_provider_init(&emc->provider);
1034 icc_node_add(node, &emc->provider);
1049 icc_node_add(node, &emc->provider);
1051 err = icc_provider_register(&emc->provider);
1058 icc_nodes_remove(&emc->provider);
1060 dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
1072 struct tegra_emc *emc = data;
1074 clk_notifier_unregister(emc->clk, &emc->clk_nb);
1077 static int tegra_emc_init_clk(struct tegra_emc *emc)
1081 tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
1083 err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback,
1088 emc->clk = devm_clk_get(emc->dev, NULL);
1089 if (IS_ERR(emc->clk)) {
1090 dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk);
1091 return PTR_ERR(emc->clk);
1094 err = clk_notifier_register(emc->clk, &emc->clk_nb);
1096 dev_err(emc->dev, "failed to register clk notifier: %d\n", err);
1100 err = devm_add_action_or_reset(emc->dev,
1101 devm_tegra_emc_unreg_clk_notifier, emc);
1111 struct tegra_emc *emc = dev_get_drvdata(dev);
1124 return emc_set_min_rate(emc, rate, EMC_RATE_DEVFREQ);
1130 struct tegra_emc *emc = dev_get_drvdata(dev);
1133 writel_relaxed(EMC_PWR_GATHER_DISABLE, emc->regs + EMC_STAT_CONTROL);
1139 stat->busy_time = readl_relaxed(emc->regs + EMC_STAT_PWR_COUNT);
1140 stat->total_time = readl_relaxed(emc->regs + EMC_STAT_PWR_CLOCKS);
1141 stat->current_frequency = clk_get_rate(emc->clk);
1144 writel_relaxed(EMC_PWR_GATHER_CLEAR, emc->regs + EMC_STAT_CONTROL);
1145 writel_relaxed(EMC_PWR_GATHER_ENABLE, emc->regs + EMC_STAT_CONTROL);
1156 static int tegra_emc_devfreq_init(struct tegra_emc *emc)
1167 emc->ondemand_data.upthreshold = 20;
1174 writel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL);
1175 writel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL);
1176 writel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT);
1178 devfreq = devm_devfreq_add_device(emc->dev, &tegra_emc_devfreq_profile,
1180 &emc->ondemand_data);
1182 dev_err(emc->dev, "failed to initialize devfreq: %pe", devfreq);
1193 struct tegra_emc *emc;
1202 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1203 if (!emc)
1206 mutex_init(&emc->rate_lock);
1207 emc->clk_nb.notifier_call = tegra_emc_clk_change_notify;
1208 emc->dev = &pdev->dev;
1210 emc->regs = devm_platform_ioremap_resource(pdev, 0);
1211 if (IS_ERR(emc->regs))
1212 return PTR_ERR(emc->regs);
1214 err = emc_setup_hw(emc);
1218 np = tegra_emc_find_node_by_ram_code(emc);
1220 err = tegra_emc_load_timings_from_dt(emc, np);
1227 dev_name(&pdev->dev), emc);
1233 err = tegra_emc_init_clk(emc);
1243 platform_set_drvdata(pdev, emc);
1244 tegra_emc_rate_requests_init(emc);
1245 tegra_emc_debugfs_init(emc);
1246 tegra_emc_interconnect_init(emc);
1247 tegra_emc_devfreq_init(emc);
1260 { .compatible = "nvidia,tegra20-emc", },
1268 .name = "tegra20-emc",