Lines Matching defs:timing
539 dev_err(emc->dev, "timing update timed out\n");
577 struct emc_timing *timing = NULL;
582 timing = &emc->timings[i];
587 if (!timing) {
588 dev_err(emc->dev, "no timing for rate %lu\n", rate);
592 return timing;
598 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
606 if (!timing)
609 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1))
611 else if (timing->emc_mode_1 & 0x1)
643 if (!(timing->emc_bgbias_ctl0 &
663 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE &&
669 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE &&
688 if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) {
690 writel(timing->emc_ctt_term_ctrl,
696 for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i)
697 writel(timing->emc_burst_data[i],
700 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2);
701 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL);
703 tegra_mc_write_emem_configuration(emc->mc, timing->rate);
705 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK;
709 if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2)
710 emc_ccfifo_writel(emc, timing->emc_auto_cal_config2,
713 if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3)
714 emc_ccfifo_writel(emc, timing->emc_auto_cal_config3,
717 if (timing->emc_auto_cal_config != last->emc_auto_cal_config) {
718 val = timing->emc_auto_cal_config;
728 if (timing->emc_zcal_interval != 0 &&
732 val = (timing->emc_mrs_wait_cnt
738 val = timing->emc_mrs_wait_cnt
746 val = timing->emc_cfg_2;
752 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
775 if (timing->emc_mode_1 != last->emc_mode_1)
776 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
777 if (timing->emc_mode_2 != last->emc_mode_2)
778 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2);
780 if ((timing->emc_mode_reset != last->emc_mode_reset) ||
782 val = timing->emc_mode_reset;
792 if (timing->emc_mode_2 != last->emc_mode_2)
793 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2);
794 if (timing->emc_mode_1 != last->emc_mode_1)
795 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW);
796 if (timing->emc_mode_4 != last->emc_mode_4)
797 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4);
801 if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) {
811 if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR)
812 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2);
826 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
830 if (!timing)
837 if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl)
838 writel(timing->emc_auto_cal_interval,
842 if (timing->emc_cfg & EMC_CFG_PWR_MASK)
843 writel(timing->emc_cfg, emc->regs + EMC_CFG);
846 writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT);
850 timing->emc_bgbias_ctl0 &
852 val = timing->emc_bgbias_ctl0;
859 timing->emc_bgbias_ctl0) {
860 writel(timing->emc_bgbias_ctl0,
864 writel(timing->emc_auto_cal_interval,
868 /* Wait for timing to settle */
872 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL);
875 emc->last_timing = *timing;
881 struct emc_timing *timing)
886 timing->emc_burst_data[i] =
889 timing->emc_cfg = readl(emc->regs + EMC_CFG);
891 timing->emc_auto_cal_interval = 0;
892 timing->emc_zcal_cnt_long = 0;
893 timing->emc_mode_1 = 0;
894 timing->emc_mode_2 = 0;
895 timing->emc_mode_4 = 0;
896 timing->emc_mode_reset = 0;
921 struct emc_timing *timing,
929 dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n",
934 timing->rate = value;
937 timing->emc_burst_data,
938 ARRAY_SIZE(timing->emc_burst_data));
941 "timing %pOFn: failed to read emc burst data: %d\n",
947 err = of_property_read_u32(node, dtprop, &timing->prop); \
949 dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \
996 struct emc_timing *timing;
1000 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
1008 timing = &emc->timings[i++];
1010 err = load_one_timing_from_dt(emc, timing, child);
1017 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,