Lines Matching defs:rate
447 unsigned long rate;
508 * a min/max clock rate, these rates are contained in this array.
512 /* protect shared rate-change code path */
575 unsigned long rate)
581 if (emc->timings[i].rate == rate) {
588 dev_err(emc->dev, "no timing for rate %lu\n", rate);
596 unsigned long rate)
598 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
703 tegra_mc_write_emem_configuration(emc->mc, timing->rate);
824 unsigned long rate)
826 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
929 dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n",
934 timing->rate = value;
983 if (a->rate < b->rate)
985 else if (a->rate == b->rate)
1087 * EMC rate-changes should go via OPP API because it manages voltage
1100 static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
1107 ret = emc_request_rate(emc, rate, req->max_rate, type);
1113 static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
1120 ret = emc_request_rate(emc, req->min_rate, rate, type);
1151 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
1156 if (rate == emc->timings[i].rate)
1170 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
1181 static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
1185 *rate = emc->debugfs.min_rate;
1190 static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
1195 if (!tegra_emc_validate_rate(emc, rate))
1198 err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
1202 emc->debugfs.min_rate = rate;
1211 static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
1215 *rate = emc->debugfs.max_rate;
1220 static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
1225 if (!tegra_emc_validate_rate(emc, rate))
1228 err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
1232 emc->debugfs.max_rate = rate;
1250 if (emc->timings[i].rate < emc->debugfs.min_rate)
1251 emc->debugfs.min_rate = emc->timings[i].rate;
1253 if (emc->timings[i].rate > emc->debugfs.max_rate)
1254 emc->debugfs.max_rate = emc->timings[i].rate;
1265 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
1321 unsigned long long rate = max(avg_bw, peak_bw);
1327 * Tegra124 EMC runs on a clock rate of SDRAM bus. This means that
1328 * EMC clock rate is twice smaller than the peak data rate because
1332 do_div(rate, ddr * dram_data_bus_width_bytes);
1333 rate = min_t(u64, rate, U32_MAX);
1335 err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
1417 dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
1420 /* first dummy rate-set initializes voltage state */