Lines Matching defs:emc
518 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value,
521 writel(value, emc->regs + EMC_CCFIFO_DATA);
522 writel(offset, emc->regs + EMC_CCFIFO_ADDR);
525 static void emc_seq_update_timing(struct tegra_emc *emc)
530 writel(1, emc->regs + EMC_TIMING_CONTROL);
533 value = readl(emc->regs + EMC_STATUS);
539 dev_err(emc->dev, "timing update timed out\n");
542 static void emc_seq_disable_auto_cal(struct tegra_emc *emc)
547 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
550 value = readl(emc->regs + EMC_AUTO_CAL_STATUS);
556 dev_err(emc->dev, "auto cal disable timed out\n");
559 static void emc_seq_wait_clkchange(struct tegra_emc *emc)
565 value = readl(emc->regs + EMC_INTSTATUS);
571 dev_err(emc->dev, "clock change timed out\n");
574 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
580 for (i = 0; i < emc->num_timings; i++) {
581 if (emc->timings[i].rate == rate) {
582 timing = &emc->timings[i];
588 dev_err(emc->dev, "no timing for rate %lu\n", rate);
595 static int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
598 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
599 struct emc_timing *last = &emc->last_timing;
617 writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS);
620 val = readl(emc->regs + EMC_CFG);
623 writel(val, emc->regs + EMC_CFG);
629 if (emc->dram_type == DRAM_TYPE_DDR3)
634 val = readl(emc->regs + EMC_SEL_DPD_CTRL);
637 writel(val, emc->regs + EMC_SEL_DPD_CTRL);
641 val = readl(emc->regs + EMC_BGBIAS_CTL0);
656 writel(val2, emc->regs + EMC_BGBIAS_CTL0);
662 val = readl(emc->regs + EMC_XM2DQSPADCTRL2);
676 writel(val, emc->regs + EMC_XM2DQSPADCTRL2);
683 emc_seq_update_timing(emc);
689 emc_seq_disable_auto_cal(emc);
691 emc->regs + EMC_CTT_TERM_CTRL);
692 emc_seq_update_timing(emc);
698 emc->regs + emc_burst_regs[i]);
700 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2);
701 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL);
703 tegra_mc_write_emem_configuration(emc->mc, timing->rate);
706 emc_ccfifo_writel(emc, val, EMC_CFG);
710 emc_ccfifo_writel(emc, timing->emc_auto_cal_config2,
714 emc_ccfifo_writel(emc, timing->emc_auto_cal_config3,
720 emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG);
724 if (emc->dram_type == DRAM_TYPE_DDR3 &&
730 cnt -= emc->dram_num * 256;
743 writel(val, emc->regs + EMC_MRS_WAIT_CNT);
748 emc_ccfifo_writel(emc, val, EMC_CFG_2);
751 if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF)
752 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
755 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num),
757 if (emc->dram_type == DRAM_TYPE_DDR3)
758 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) |
763 emc_ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
766 if (emc->dram_type == DRAM_TYPE_DDR3)
767 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num),
769 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) |
774 if (emc->dram_type == DRAM_TYPE_DDR3) {
776 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
778 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2);
789 emc_ccfifo_writel(emc, val, EMC_MRS);
793 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2);
795 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW);
797 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4);
802 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL);
803 if (emc->dram_num > 1)
804 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV1,
809 emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS);
812 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2);
815 emc_seq_disable_auto_cal(emc);
818 readl(emc->regs + EMC_INTSTATUS);
823 static void tegra_emc_complete_timing_change(struct tegra_emc *emc,
826 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
827 struct emc_timing *last = &emc->last_timing;
834 emc_seq_wait_clkchange(emc);
839 emc->regs + EMC_AUTO_CAL_INTERVAL);
843 writel(timing->emc_cfg, emc->regs + EMC_CFG);
846 writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT);
849 if (emc->dram_type == DRAM_TYPE_LPDDR3 &&
855 writel(val, emc->regs + EMC_BGBIAS_CTL0);
857 if (emc->dram_type == DRAM_TYPE_DDR3 &&
858 readl(emc->regs + EMC_BGBIAS_CTL0) !=
861 emc->regs + EMC_BGBIAS_CTL0);
865 emc->regs + EMC_AUTO_CAL_INTERVAL);
872 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL);
873 emc_seq_update_timing(emc);
875 emc->last_timing = *timing;
880 static void emc_read_current_timing(struct tegra_emc *emc,
887 readl(emc->regs + emc_burst_regs[i]);
889 timing->emc_cfg = readl(emc->regs + EMC_CFG);
899 static int emc_init(struct tegra_emc *emc)
901 emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5);
903 if (emc->dram_type & EMC_FBIO_CFG5_DRAM_WIDTH_X64)
904 emc->dram_bus_width = 64;
906 emc->dram_bus_width = 32;
908 dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
910 emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK;
911 emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT;
913 emc->dram_num = tegra_mc_get_emem_device_count(emc->mc);
915 emc_read_current_timing(emc, &emc->last_timing);
920 static int load_one_timing_from_dt(struct tegra_emc *emc,
929 dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n",
936 err = of_property_read_u32_array(node, "nvidia,emc-configuration",
940 dev_err(emc->dev,
941 "timing %pOFn: failed to read emc burst data: %d\n",
949 dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \
955 EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config")
956 EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2")
957 EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3")
958 EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
959 EMC_READ_PROP(emc_bgbias_ctl0, "nvidia,emc-bgbias-ctl0")
960 EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg")
961 EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2")
962 EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl")
963 EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1")
964 EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2")
965 EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4")
966 EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset")
967 EMC_READ_PROP(emc_mrs_wait_cnt, "nvidia,emc-mrs-wait-cnt")
968 EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl")
969 EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2")
970 EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
971 EMC_READ_PROP(emc_zcal_interval, "nvidia,emc-zcal-interval")
991 static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
1000 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
1002 if (!emc->timings)
1005 emc->num_timings = child_count;
1008 timing = &emc->timings[i++];
1010 err = load_one_timing_from_dt(emc, timing, child);
1017 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
1024 { .compatible = "nvidia,tegra124-emc" },
1025 { .compatible = "nvidia,tegra132-emc" },
1049 static void tegra_emc_rate_requests_init(struct tegra_emc *emc)
1054 emc->requested_rate[i].min_rate = 0;
1055 emc->requested_rate[i].max_rate = ULONG_MAX;
1059 static int emc_request_rate(struct tegra_emc *emc,
1064 struct emc_rate_request *req = emc->requested_rate;
1081 dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
1090 err = dev_pm_opp_set_rate(emc->dev, min_rate);
1094 emc->requested_rate[type].min_rate = new_min_rate;
1095 emc->requested_rate[type].max_rate = new_max_rate;
1100 static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
1103 struct emc_rate_request *req = &emc->requested_rate[type];
1106 mutex_lock(&emc->rate_lock);
1107 ret = emc_request_rate(emc, rate, req->max_rate, type);
1108 mutex_unlock(&emc->rate_lock);
1113 static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
1116 struct emc_rate_request *req = &emc->requested_rate[type];
1119 mutex_lock(&emc->rate_lock);
1120 ret = emc_request_rate(emc, req->min_rate, rate, type);
1121 mutex_unlock(&emc->rate_lock);
1132 * /sys/kernel/debug/emc
1151 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
1155 for (i = 0; i < emc->num_timings; i++)
1156 if (rate == emc->timings[i].rate)
1165 struct tegra_emc *emc = s->private;
1169 for (i = 0; i < emc->num_timings; i++) {
1170 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
1183 struct tegra_emc *emc = data;
1185 *rate = emc->debugfs.min_rate;
1192 struct tegra_emc *emc = data;
1195 if (!tegra_emc_validate_rate(emc, rate))
1198 err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
1202 emc->debugfs.min_rate = rate;
1213 struct tegra_emc *emc = data;
1215 *rate = emc->debugfs.max_rate;
1222 struct tegra_emc *emc = data;
1225 if (!tegra_emc_validate_rate(emc, rate))
1228 err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
1232 emc->debugfs.max_rate = rate;
1241 static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc)
1246 emc->debugfs.min_rate = ULONG_MAX;
1247 emc->debugfs.max_rate = 0;
1249 for (i = 0; i < emc->num_timings; i++) {
1250 if (emc->timings[i].rate < emc->debugfs.min_rate)
1251 emc->debugfs.min_rate = emc->timings[i].rate;
1253 if (emc->timings[i].rate > emc->debugfs.max_rate)
1254 emc->debugfs.max_rate = emc->timings[i].rate;
1257 if (!emc->num_timings) {
1258 emc->debugfs.min_rate = clk_get_rate(emc->clk);
1259 emc->debugfs.max_rate = emc->debugfs.min_rate;
1262 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
1263 emc->debugfs.max_rate);
1266 emc->debugfs.min_rate, emc->debugfs.max_rate,
1267 emc->clk);
1271 emc->debugfs.root = debugfs_create_dir("emc", NULL);
1273 debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc,
1275 debugfs_create_file("min_rate", 0644, emc->debugfs.root,
1276 emc, &tegra_emc_debug_min_rate_fops);
1277 debugfs_create_file("max_rate", 0644, emc->debugfs.root,
1278 emc, &tegra_emc_debug_max_rate_fops);
1318 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
1331 dram_data_bus_width_bytes = emc->dram_bus_width / 8;
1335 err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
1342 static int tegra_emc_interconnect_init(struct tegra_emc *emc)
1344 const struct tegra_mc_soc *soc = emc->mc->soc;
1348 emc->provider.dev = emc->dev;
1349 emc->provider.set = emc_icc_set;
1350 emc->provider.data = &emc->provider;
1351 emc->provider.aggregate = soc->icc_ops->aggregate;
1352 emc->provider.xlate_extended = emc_of_icc_xlate_extended;
1354 icc_provider_init(&emc->provider);
1364 icc_node_add(node, &emc->provider);
1379 icc_node_add(node, &emc->provider);
1381 err = icc_provider_register(&emc->provider);
1388 icc_nodes_remove(&emc->provider);
1390 dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
1395 static int tegra_emc_opp_table_init(struct tegra_emc *emc)
1400 err = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1);
1402 dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err);
1407 err = dev_pm_opp_of_add_table(emc->dev);
1410 dev_err(emc->dev, "OPP table not found, please update your device tree\n");
1412 dev_err(emc->dev, "failed to add OPP table: %d\n", err);
1417 dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
1418 hw_version, clk_get_rate(emc->clk) / 1000000);
1421 err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));
1423 dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err);
1430 dev_pm_opp_of_remove_table(emc->dev);
1445 struct tegra_emc *emc;
1449 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1450 if (!emc)
1453 mutex_init(&emc->rate_lock);
1454 emc->dev = &pdev->dev;
1456 emc->regs = devm_platform_ioremap_resource(pdev, 0);
1457 if (IS_ERR(emc->regs))
1458 return PTR_ERR(emc->regs);
1460 emc->mc = devm_tegra_memory_controller_get(&pdev->dev);
1461 if (IS_ERR(emc->mc))
1462 return PTR_ERR(emc->mc);
1468 err = tegra_emc_load_timings_from_dt(emc, np);
1478 err = emc_init(emc);
1484 platform_set_drvdata(pdev, emc);
1494 emc->clk = devm_clk_get(&pdev->dev, "emc");
1495 if (IS_ERR(emc->clk)) {
1496 err = PTR_ERR(emc->clk);
1501 err = tegra_emc_opp_table_init(emc);
1505 tegra_emc_rate_requests_init(emc);
1508 emc_debugfs_init(&pdev->dev, emc);
1510 tegra_emc_interconnect_init(emc);
1525 .name = "tegra-emc",