Lines Matching defs:node
67 * This function will search for the Memory Controller node in a device-tree
420 struct device_node *node)
425 err = of_property_read_u32(node, "clock-frequency", &tmp);
428 "timing %pOFn: failed to read rate\n", node);
438 err = of_property_read_u32_array(node, "nvidia,emem-configuration",
444 node);
451 static int load_timings(struct tegra_mc *mc, struct device_node *node)
455 int child_count = of_get_child_count(node);
465 for_each_child_of_node(node, child) {
480 struct device_node *node;
488 for_each_child_of_node(mc->dev->of_node, node) {
489 err = of_property_read_u32(node, "nvidia,ram-code",
494 err = load_timings(mc, node);
495 of_node_put(node);
761 struct icc_node *node;
763 list_for_each_entry(node, &mc->provider.nodes, node_list) {
764 if (node->id == spec->args[0])
765 return node;
775 static int tegra_mc_icc_get(struct icc_node *node, u32 *average, u32 *peak)
801 * to the required bandwidth. Each MC interconnect node represents an
820 struct icc_node *node;
839 /* create Memory Controller node */
840 node = icc_node_create(TEGRA_ICC_MC);
841 if (IS_ERR(node))
842 return PTR_ERR(node);
844 node->name = "Memory Controller";
845 icc_node_add(node, &mc->provider);
848 err = icc_link_create(node, TEGRA_ICC_EMC);
853 /* create MC client node */
854 node = icc_node_create(mc->soc->clients[i].id);
855 if (IS_ERR(node)) {
856 err = PTR_ERR(node);
860 node->name = mc->soc->clients[i].name;
861 icc_node_add(node, &mc->provider);
864 err = icc_link_create(node, TEGRA_ICC_MC);
868 node->data = (struct tegra_mc_client *)&(mc->soc->clients[i]);