Lines Matching refs:val
203 unsigned int val;
842 u32 val;
852 val = readl(dmc->base_drexi0 + DREX_FLAG_PPC);
853 if (val) {
856 dev_dbg(dmc->dev, "drex0 0xE050 val= 0x%08x\n", val);
858 val = readl(dmc->base_drexi1 + DREX_FLAG_PPC);
861 dev_dbg(dmc->dev, "drex1 0xE050 val= 0x%08x\n", val);
1040 u32 val;
1050 val = dmc->timings->tRFC / clk_period_ps;
1051 val += dmc->timings->tRFC % clk_period_ps ? 1 : 0;
1052 val = max(val, dmc->min_tck->tRFC);
1054 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1056 val = dmc->timings->tRRD / clk_period_ps;
1057 val += dmc->timings->tRRD % clk_period_ps ? 1 : 0;
1058 val = max(val, dmc->min_tck->tRRD);
1060 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1062 val = dmc->timings->tRPab / clk_period_ps;
1063 val += dmc->timings->tRPab % clk_period_ps ? 1 : 0;
1064 val = max(val, dmc->min_tck->tRPab);
1066 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1068 val = dmc->timings->tRCD / clk_period_ps;
1069 val += dmc->timings->tRCD % clk_period_ps ? 1 : 0;
1070 val = max(val, dmc->min_tck->tRCD);
1072 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1074 val = dmc->timings->tRC / clk_period_ps;
1075 val += dmc->timings->tRC % clk_period_ps ? 1 : 0;
1076 val = max(val, dmc->min_tck->tRC);
1078 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1080 val = dmc->timings->tRAS / clk_period_ps;
1081 val += dmc->timings->tRAS % clk_period_ps ? 1 : 0;
1082 val = max(val, dmc->min_tck->tRAS);
1084 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1087 val = dmc->timings->tWTR / clk_period_ps;
1088 val += dmc->timings->tWTR % clk_period_ps ? 1 : 0;
1089 val = max(val, dmc->min_tck->tWTR);
1091 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1093 val = dmc->timings->tWR / clk_period_ps;
1094 val += dmc->timings->tWR % clk_period_ps ? 1 : 0;
1095 val = max(val, dmc->min_tck->tWR);
1097 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1099 val = dmc->timings->tRTP / clk_period_ps;
1100 val += dmc->timings->tRTP % clk_period_ps ? 1 : 0;
1101 val = max(val, dmc->min_tck->tRTP);
1103 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1105 val = dmc->timings->tW2W_C2C / clk_period_ps;
1106 val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0;
1107 val = max(val, dmc->min_tck->tW2W_C2C);
1109 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1111 val = dmc->timings->tR2R_C2C / clk_period_ps;
1112 val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0;
1113 val = max(val, dmc->min_tck->tR2R_C2C);
1115 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1117 val = dmc->timings->tWL / clk_period_ps;
1118 val += dmc->timings->tWL % clk_period_ps ? 1 : 0;
1119 val = max(val, dmc->min_tck->tWL);
1121 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1123 val = dmc->timings->tDQSCK / clk_period_ps;
1124 val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0;
1125 val = max(val, dmc->min_tck->tDQSCK);
1127 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1129 val = dmc->timings->tRL / clk_period_ps;
1130 val += dmc->timings->tRL % clk_period_ps ? 1 : 0;
1131 val = max(val, dmc->min_tck->tRL);
1133 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1136 val = dmc->timings->tFAW / clk_period_ps;
1137 val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
1138 val = max(val, dmc->min_tck->tFAW);
1140 *reg_timing_power |= TIMING_VAL2REG(reg, val);
1142 val = dmc->timings->tXSR / clk_period_ps;
1143 val += dmc->timings->tXSR % clk_period_ps ? 1 : 0;
1144 val = max(val, dmc->min_tck->tXSR);
1146 *reg_timing_power |= TIMING_VAL2REG(reg, val);
1148 val = dmc->timings->tXP / clk_period_ps;
1149 val += dmc->timings->tXP % clk_period_ps ? 1 : 0;
1150 val = max(val, dmc->min_tck->tXP);
1152 *reg_timing_power |= TIMING_VAL2REG(reg, val);
1154 val = dmc->timings->tCKE / clk_period_ps;
1155 val += dmc->timings->tCKE % clk_period_ps ? 1 : 0;
1156 val = max(val, dmc->min_tck->tCKE);
1158 *reg_timing_power |= TIMING_VAL2REG(reg, val);
1160 val = dmc->timings->tMRD / clk_period_ps;
1161 val += dmc->timings->tMRD % clk_period_ps ? 1 : 0;
1162 val = max(val, dmc->min_tck->tMRD);
1164 *reg_timing_power |= TIMING_VAL2REG(reg, val);
1381 unsigned int val;
1384 ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val);
1388 val |= 1UL;
1389 regmap_write(dmc->clk_regmap, CDREX_PAUSE, val);