Lines Matching defs:dmc
238 static int exynos5_counters_set_event(struct exynos5_dmc *dmc)
242 for (i = 0; i < dmc->num_counters; i++) {
243 if (!dmc->counter[i])
245 ret = devfreq_event_set_event(dmc->counter[i]);
252 static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc)
256 for (i = 0; i < dmc->num_counters; i++) {
257 if (!dmc->counter[i])
259 ret = devfreq_event_enable_edev(dmc->counter[i]);
266 static int exynos5_counters_disable_edev(struct exynos5_dmc *dmc)
270 for (i = 0; i < dmc->num_counters; i++) {
271 if (!dmc->counter[i])
273 ret = devfreq_event_disable_edev(dmc->counter[i]);
282 * @dmc: device for which the information is checked
288 static int find_target_freq_idx(struct exynos5_dmc *dmc,
293 for (i = dmc->opp_count - 1; i >= 0; i--)
294 if (dmc->opp[i].freq_hz <= target_rate)
302 * @dmc: device for which the new settings is going to be applied
313 static int exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set)
318 ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, ®);
327 regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg);
334 * @dmc: DMC device for which the frequencies are used for OPP init
339 static int exynos5_init_freq_table(struct exynos5_dmc *dmc,
346 ret = devm_pm_opp_of_add_table(dmc->dev);
348 dev_err(dmc->dev, "Failed to get OPP table\n");
352 dmc->opp_count = dev_pm_opp_get_opp_count(dmc->dev);
354 dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count,
356 if (!dmc->opp)
359 idx = dmc->opp_count - 1;
360 for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) {
363 opp = dev_pm_opp_find_freq_floor(dmc->dev, &freq);
367 dmc->opp[idx - i].freq_hz = freq;
368 dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp);
378 * @dmc: device for which the new settings is going to be applied
384 static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc)
387 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
389 writel(dmc->bypass_timing_row,
390 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1);
391 writel(dmc->bypass_timing_row,
392 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1);
393 writel(dmc->bypass_timing_data,
394 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1);
395 writel(dmc->bypass_timing_data,
396 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1);
397 writel(dmc->bypass_timing_power,
398 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1);
399 writel(dmc->bypass_timing_power,
400 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1);
405 * @dmc: device for which the new settings is going to be applied
414 static int exynos5_dram_change_timings(struct exynos5_dmc *dmc,
419 for (idx = dmc->opp_count - 1; idx >= 0; idx--)
420 if (dmc->opp[idx].freq_hz <= target_rate)
427 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
429 writel(dmc->timing_row[idx],
430 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0);
431 writel(dmc->timing_row[idx],
432 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0);
433 writel(dmc->timing_data[idx],
434 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0);
435 writel(dmc->timing_data[idx],
436 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0);
437 writel(dmc->timing_power[idx],
438 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0);
439 writel(dmc->timing_power[idx],
440 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0);
447 * @dmc: device for which it is going to be set
455 static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc,
460 if (dmc->curr_volt <= target_volt)
463 ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
466 dmc->curr_volt = target_volt;
473 * @dmc: device for which it is going to be set
481 static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc,
486 if (dmc->curr_volt >= target_volt)
489 ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
492 dmc->curr_volt = target_volt;
499 * @dmc: device for which it is going to be set
504 static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc,
507 int idx = find_target_freq_idx(dmc, target_rate);
512 exynos5_set_bypass_dram_timings(dmc);
519 * @dmc: DMC device for which the switching is going to happen
529 exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc,
540 ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt);
547 ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate);
554 ret = exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS);
562 * @dmc: device for which the frequency is going to be changed
583 exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc,
589 ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate,
598 clk_prepare_enable(dmc->fout_spll);
599 clk_prepare_enable(dmc->mout_spll);
600 clk_prepare_enable(dmc->mout_mx_mspll_ccore);
602 ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore);
611 exynos5_dram_change_timings(dmc, target_rate);
613 clk_set_rate(dmc->fout_bpll, target_rate);
615 ret = exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS);
619 ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll);
627 ret = exynos5_dmc_align_target_voltage(dmc, target_volt);
630 clk_disable_unprepare(dmc->mout_mx_mspll_ccore);
631 clk_disable_unprepare(dmc->mout_spll);
632 clk_disable_unprepare(dmc->fout_spll);
640 * @dmc: device for which the frequency is going to be changed
652 static int exynos5_dmc_get_volt_freq(struct exynos5_dmc *dmc,
659 opp = devfreq_recommended_opp(dmc->dev, freq, flags);
685 struct exynos5_dmc *dmc = dev_get_drvdata(dev);
690 ret = exynos5_dmc_get_volt_freq(dmc, freq, &target_rate, &target_volt,
696 if (target_rate == dmc->curr_rate)
699 mutex_lock(&dmc->lock);
701 ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt);
704 mutex_unlock(&dmc->lock);
708 dmc->curr_rate = target_rate;
710 mutex_unlock(&dmc->lock);
716 * @dmc: device for which the counters are going to be checked
724 static int exynos5_counters_get(struct exynos5_dmc *dmc,
735 for (i = 0; i < dmc->num_counters; i++) {
736 if (!dmc->counter[i])
739 ret = devfreq_event_get_event(dmc->counter[i], &event);
756 * @dmc: device for which the counters are going to be checked
762 static void exynos5_dmc_start_perf_events(struct exynos5_dmc *dmc,
766 writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENS_PPC);
767 writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENS_PPC);
770 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENS_PPC);
771 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENS_PPC);
774 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);
775 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC);
778 writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi0 + DREX_PMNC_PPC);
779 writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi1 + DREX_PMNC_PPC);
785 writel(beg_value, dmc->base_drexi0 + DREX_PMCNT2_PPC);
786 writel(beg_value, dmc->base_drexi1 + DREX_PMCNT2_PPC);
789 writel(PPC_ENABLE, dmc->base_drexi0 + DREX_PMNC_PPC);
790 writel(PPC_ENABLE, dmc->base_drexi1 + DREX_PMNC_PPC);
795 * @dmc: device for which the counters are going to be checked
802 static void exynos5_dmc_perf_events_calc(struct exynos5_dmc *dmc, u64 diff_ts)
819 dmc->load = 70;
820 dmc->total = 100;
826 dmc->load = 35;
827 dmc->total = 100;
830 dev_dbg(dmc->dev, "diff_ts=%llu\n", diff_ts);
835 * @dmc: device for which the counters are going to be checked
840 static void exynos5_dmc_perf_events_check(struct exynos5_dmc *dmc)
848 writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);
849 writel(0, dmc->base_drexi1 + DREX_PMNC_PPC);
852 val = readl(dmc->base_drexi0 + DREX_FLAG_PPC);
854 diff_ts = ts - dmc->last_overflow_ts[0];
855 dmc->last_overflow_ts[0] = ts;
856 dev_dbg(dmc->dev, "drex0 0xE050 val= 0x%08x\n", val);
858 val = readl(dmc->base_drexi1 + DREX_FLAG_PPC);
859 diff_ts = ts - dmc->last_overflow_ts[1];
860 dmc->last_overflow_ts[1] = ts;
861 dev_dbg(dmc->dev, "drex1 0xE050 val= 0x%08x\n", val);
864 exynos5_dmc_perf_events_calc(dmc, diff_ts);
866 exynos5_dmc_start_perf_events(dmc, PERF_COUNTER_START_VALUE);
871 * @dmc: device for which the counters are going to be checked
875 static void exynos5_dmc_enable_perf_events(struct exynos5_dmc *dmc)
880 writel(PEREV_CLK_EN, dmc->base_drexi0 + DREX_PPCCLKCON);
881 writel(PEREV_CLK_EN, dmc->base_drexi1 + DREX_PPCCLKCON);
884 writel(READ_TRANSFER_CH0, dmc->base_drexi0 + DREX_PEREV2CONFIG);
885 writel(READ_TRANSFER_CH1, dmc->base_drexi1 + DREX_PEREV2CONFIG);
888 dmc->last_overflow_ts[0] = ts;
889 dmc->last_overflow_ts[1] = ts;
892 dmc->load = 99;
893 dmc->total = 100;
898 * @dmc: device for which the counters are going to be checked
902 static void exynos5_dmc_disable_perf_events(struct exynos5_dmc *dmc)
905 writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);
906 writel(0, dmc->base_drexi1 + DREX_PMNC_PPC);
909 writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENC_PPC);
910 writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENC_PPC);
913 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENC_PPC);
914 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENC_PPC);
917 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);
918 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC);
933 struct exynos5_dmc *dmc = dev_get_drvdata(dev);
937 if (dmc->in_irq_mode) {
938 mutex_lock(&dmc->lock);
939 stat->current_frequency = dmc->curr_rate;
940 mutex_unlock(&dmc->lock);
942 stat->busy_time = dmc->load;
943 stat->total_time = dmc->total;
945 ret = exynos5_counters_get(dmc, &load, &total);
953 ret = exynos5_counters_set_event(dmc);
974 struct exynos5_dmc *dmc = dev_get_drvdata(dev);
976 mutex_lock(&dmc->lock);
977 *freq = dmc->curr_rate;
978 mutex_unlock(&dmc->lock);
997 * @dmc: device for which the frequency is going to be set
1008 exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc,
1014 idx = find_target_freq_idx(dmc, bootloader_init_freq);
1016 aligned_freq = dmc->opp[idx].freq_hz;
1018 aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz;
1025 * @dmc: device for which the frequency is going to be set
1036 static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row,
1050 val = dmc->timings->tRFC / clk_period_ps;
1051 val += dmc->timings->tRFC % clk_period_ps ? 1 : 0;
1052 val = max(val, dmc->min_tck->tRFC);
1056 val = dmc->timings->tRRD / clk_period_ps;
1057 val += dmc->timings->tRRD % clk_period_ps ? 1 : 0;
1058 val = max(val, dmc->min_tck->tRRD);
1062 val = dmc->timings->tRPab / clk_period_ps;
1063 val += dmc->timings->tRPab % clk_period_ps ? 1 : 0;
1064 val = max(val, dmc->min_tck->tRPab);
1068 val = dmc->timings->tRCD / clk_period_ps;
1069 val += dmc->timings->tRCD % clk_period_ps ? 1 : 0;
1070 val = max(val, dmc->min_tck->tRCD);
1074 val = dmc->timings->tRC / clk_period_ps;
1075 val += dmc->timings->tRC % clk_period_ps ? 1 : 0;
1076 val = max(val, dmc->min_tck->tRC);
1080 val = dmc->timings->tRAS / clk_period_ps;
1081 val += dmc->timings->tRAS % clk_period_ps ? 1 : 0;
1082 val = max(val, dmc->min_tck->tRAS);
1087 val = dmc->timings->tWTR / clk_period_ps;
1088 val += dmc->timings->tWTR % clk_period_ps ? 1 : 0;
1089 val = max(val, dmc->min_tck->tWTR);
1093 val = dmc->timings->tWR / clk_period_ps;
1094 val += dmc->timings->tWR % clk_period_ps ? 1 : 0;
1095 val = max(val, dmc->min_tck->tWR);
1099 val = dmc->timings->tRTP / clk_period_ps;
1100 val += dmc->timings->tRTP % clk_period_ps ? 1 : 0;
1101 val = max(val, dmc->min_tck->tRTP);
1105 val = dmc->timings->tW2W_C2C / clk_period_ps;
1106 val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0;
1107 val = max(val, dmc->min_tck->tW2W_C2C);
1111 val = dmc->timings->tR2R_C2C / clk_period_ps;
1112 val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0;
1113 val = max(val, dmc->min_tck->tR2R_C2C);
1117 val = dmc->timings->tWL / clk_period_ps;
1118 val += dmc->timings->tWL % clk_period_ps ? 1 : 0;
1119 val = max(val, dmc->min_tck->tWL);
1123 val = dmc->timings->tDQSCK / clk_period_ps;
1124 val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0;
1125 val = max(val, dmc->min_tck->tDQSCK);
1129 val = dmc->timings->tRL / clk_period_ps;
1130 val += dmc->timings->tRL % clk_period_ps ? 1 : 0;
1131 val = max(val, dmc->min_tck->tRL);
1136 val = dmc->timings->tFAW / clk_period_ps;
1137 val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
1138 val = max(val, dmc->min_tck->tFAW);
1142 val = dmc->timings->tXSR / clk_period_ps;
1143 val += dmc->timings->tXSR % clk_period_ps ? 1 : 0;
1144 val = max(val, dmc->min_tck->tXSR);
1148 val = dmc->timings->tXP / clk_period_ps;
1149 val += dmc->timings->tXP % clk_period_ps ? 1 : 0;
1150 val = max(val, dmc->min_tck->tXP);
1154 val = dmc->timings->tCKE / clk_period_ps;
1155 val += dmc->timings->tCKE % clk_period_ps ? 1 : 0;
1156 val = max(val, dmc->min_tck->tCKE);
1160 val = dmc->timings->tMRD / clk_period_ps;
1161 val += dmc->timings->tMRD % clk_period_ps ? 1 : 0;
1162 val = max(val, dmc->min_tck->tMRD);
1171 * @dmc: device for which the frequency is going to be set
1175 static int of_get_dram_timings(struct exynos5_dmc *dmc)
1182 np_ddr = of_parse_phandle(dmc->dev->of_node, "device-handle", 0);
1184 dev_warn(dmc->dev, "could not find 'device-handle' in DT\n");
1188 dmc->timing_row = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
1190 if (!dmc->timing_row) {
1195 dmc->timing_data = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
1197 if (!dmc->timing_data) {
1202 dmc->timing_power = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
1204 if (!dmc->timing_power) {
1209 dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev,
1211 &dmc->timings_arr_size);
1212 if (!dmc->timings) {
1213 dev_warn(dmc->dev, "could not get timings from DT\n");
1218 dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dmc->dev);
1219 if (!dmc->min_tck) {
1220 dev_warn(dmc->dev, "could not get tck from DT\n");
1226 for (idx = 0; idx < dmc->opp_count; idx++) {
1227 freq_mhz = dmc->opp[idx].freq_hz / 1000000;
1230 ret = create_timings_aligned(dmc, &dmc->timing_row[idx],
1231 &dmc->timing_data[idx],
1232 &dmc->timing_power[idx],
1238 dmc->bypass_timing_row = dmc->timing_row[idx - 1];
1239 dmc->bypass_timing_data = dmc->timing_data[idx - 1];
1240 dmc->bypass_timing_power = dmc->timing_power[idx - 1];
1249 * @dmc: DMC structure containing needed fields
1254 static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc)
1261 dmc->fout_spll = devm_clk_get(dmc->dev, "fout_spll");
1262 if (IS_ERR(dmc->fout_spll))
1263 return PTR_ERR(dmc->fout_spll);
1265 dmc->fout_bpll = devm_clk_get(dmc->dev, "fout_bpll");
1266 if (IS_ERR(dmc->fout_bpll))
1267 return PTR_ERR(dmc->fout_bpll);
1269 dmc->mout_mclk_cdrex = devm_clk_get(dmc->dev, "mout_mclk_cdrex");
1270 if (IS_ERR(dmc->mout_mclk_cdrex))
1271 return PTR_ERR(dmc->mout_mclk_cdrex);
1273 dmc->mout_bpll = devm_clk_get(dmc->dev, "mout_bpll");
1274 if (IS_ERR(dmc->mout_bpll))
1275 return PTR_ERR(dmc->mout_bpll);
1277 dmc->mout_mx_mspll_ccore = devm_clk_get(dmc->dev,
1279 if (IS_ERR(dmc->mout_mx_mspll_ccore))
1280 return PTR_ERR(dmc->mout_mx_mspll_ccore);
1282 dmc->mout_spll = devm_clk_get(dmc->dev, "ff_dout_spll2");
1283 if (IS_ERR(dmc->mout_spll)) {
1284 dmc->mout_spll = devm_clk_get(dmc->dev, "mout_sclk_spll");
1285 if (IS_ERR(dmc->mout_spll))
1286 return PTR_ERR(dmc->mout_spll);
1292 dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex);
1293 dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate);
1294 exynos5_dmc_df_profile.initial_freq = dmc->curr_rate;
1296 ret = exynos5_dmc_get_volt_freq(dmc, &dmc->curr_rate, &target_rate,
1301 dmc->curr_volt = target_volt;
1303 ret = clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll);
1307 clk_prepare_enable(dmc->fout_bpll);
1308 clk_prepare_enable(dmc->mout_bpll);
1314 regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, &tmp);
1316 regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, tmp);
1323 * @dmc: DMC for which it does the setup
1330 static int exynos5_performance_counters_init(struct exynos5_dmc *dmc)
1334 dmc->num_counters = devfreq_event_get_edev_count(dmc->dev,
1336 if (dmc->num_counters < 0) {
1337 dev_err(dmc->dev, "could not get devfreq-event counters\n");
1338 return dmc->num_counters;
1341 dmc->counter = devm_kcalloc(dmc->dev, dmc->num_counters,
1342 sizeof(*dmc->counter), GFP_KERNEL);
1343 if (!dmc->counter)
1346 for (i = 0; i < dmc->num_counters; i++) {
1347 dmc->counter[i] =
1348 devfreq_event_get_edev_by_phandle(dmc->dev,
1350 if (IS_ERR_OR_NULL(dmc->counter[i]))
1354 ret = exynos5_counters_enable_edev(dmc);
1356 dev_err(dmc->dev, "could not enable event counter\n");
1360 ret = exynos5_counters_set_event(dmc);
1362 exynos5_counters_disable_edev(dmc);
1363 dev_err(dmc->dev, "could not set event counter\n");
1372 * @dmc: device which is used for changing this feature
1379 static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc)
1384 ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val);
1389 regmap_write(dmc->clk_regmap, CDREX_PAUSE, val);
1397 struct exynos5_dmc *dmc = priv;
1399 mutex_lock(&dmc->df->lock);
1400 exynos5_dmc_perf_events_check(dmc);
1401 res = update_devfreq(dmc->df);
1402 mutex_unlock(&dmc->df->lock);
1405 dev_warn(dmc->dev, "devfreq failed with %d\n", res);
1425 struct exynos5_dmc *dmc;
1428 dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL);
1429 if (!dmc)
1432 mutex_init(&dmc->lock);
1434 dmc->dev = dev;
1435 platform_set_drvdata(pdev, dmc);
1437 dmc->base_drexi0 = devm_platform_ioremap_resource(pdev, 0);
1438 if (IS_ERR(dmc->base_drexi0))
1439 return PTR_ERR(dmc->base_drexi0);
1441 dmc->base_drexi1 = devm_platform_ioremap_resource(pdev, 1);
1442 if (IS_ERR(dmc->base_drexi1))
1443 return PTR_ERR(dmc->base_drexi1);
1445 dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np,
1447 if (IS_ERR(dmc->clk_regmap))
1448 return PTR_ERR(dmc->clk_regmap);
1450 ret = exynos5_init_freq_table(dmc, &exynos5_dmc_df_profile);
1456 dmc->vdd_mif = devm_regulator_get(dev, "vdd");
1457 if (IS_ERR(dmc->vdd_mif)) {
1458 ret = PTR_ERR(dmc->vdd_mif);
1462 ret = exynos5_dmc_init_clks(dmc);
1466 ret = of_get_dram_timings(dmc);
1472 ret = exynos5_dmc_set_pause_on_switching(dmc);
1484 dev_name(dev), dmc);
1492 dev_name(dev), dmc);
1502 dmc->gov_data.upthreshold = 55;
1503 dmc->gov_data.downdifferential = 5;
1505 exynos5_dmc_enable_perf_events(dmc);
1507 dmc->in_irq_mode = 1;
1509 ret = exynos5_performance_counters_init(dmc);
1519 dmc->gov_data.upthreshold = 10;
1520 dmc->gov_data.downdifferential = 5;
1525 dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile,
1527 &dmc->gov_data);
1529 if (IS_ERR(dmc->df)) {
1530 ret = PTR_ERR(dmc->df);
1534 if (dmc->in_irq_mode)
1535 exynos5_dmc_start_perf_events(dmc, PERF_COUNTER_START_VALUE);
1537 dev_info(dev, "DMC initialized, in irq mode: %d\n", dmc->in_irq_mode);
1542 if (dmc->in_irq_mode)
1543 exynos5_dmc_disable_perf_events(dmc);
1545 exynos5_counters_disable_edev(dmc);
1547 clk_disable_unprepare(dmc->mout_bpll);
1548 clk_disable_unprepare(dmc->fout_bpll);
1563 struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev);
1565 if (dmc->in_irq_mode)
1566 exynos5_dmc_disable_perf_events(dmc);
1568 exynos5_counters_disable_edev(dmc);
1570 clk_disable_unprepare(dmc->mout_bpll);
1571 clk_disable_unprepare(dmc->fout_bpll);
1577 { .compatible = "samsung,exynos5422-dmc", },
1586 .name = "exynos5-dmc",