Lines Matching defs:base_drexi1
117 * @base_drexi1: DREX1 registers mapping
157 void __iomem *base_drexi1;
392 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1);
396 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1);
400 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1);
432 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0);
436 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0);
440 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0);
767 writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENS_PPC);
771 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENS_PPC);
775 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC);
779 writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi1 + DREX_PMNC_PPC);
786 writel(beg_value, dmc->base_drexi1 + DREX_PMCNT2_PPC);
790 writel(PPC_ENABLE, dmc->base_drexi1 + DREX_PMNC_PPC);
849 writel(0, dmc->base_drexi1 + DREX_PMNC_PPC);
858 val = readl(dmc->base_drexi1 + DREX_FLAG_PPC);
881 writel(PEREV_CLK_EN, dmc->base_drexi1 + DREX_PPCCLKCON);
885 writel(READ_TRANSFER_CH1, dmc->base_drexi1 + DREX_PEREV2CONFIG);
906 writel(0, dmc->base_drexi1 + DREX_PMNC_PPC);
910 writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENC_PPC);
914 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENC_PPC);
918 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC);
1441 dmc->base_drexi1 = devm_platform_ioremap_resource(pdev, 1);
1442 if (IS_ERR(dmc->base_drexi1))
1443 return PTR_ERR(dmc->base_drexi1);