Lines Matching defs:base_drexi0
116 * @base_drexi0: DREX0 registers mapping
156 void __iomem *base_drexi0;
387 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
390 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1);
394 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1);
398 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1);
427 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
430 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0);
434 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0);
438 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0);
766 writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENS_PPC);
770 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENS_PPC);
774 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);
778 writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi0 + DREX_PMNC_PPC);
785 writel(beg_value, dmc->base_drexi0 + DREX_PMCNT2_PPC);
789 writel(PPC_ENABLE, dmc->base_drexi0 + DREX_PMNC_PPC);
848 writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);
852 val = readl(dmc->base_drexi0 + DREX_FLAG_PPC);
880 writel(PEREV_CLK_EN, dmc->base_drexi0 + DREX_PPCCLKCON);
884 writel(READ_TRANSFER_CH0, dmc->base_drexi0 + DREX_PEREV2CONFIG);
905 writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);
909 writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENC_PPC);
913 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENC_PPC);
917 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);
1437 dmc->base_drexi0 = devm_platform_ioremap_resource(pdev, 0);
1438 if (IS_ERR(dmc->base_drexi0))
1439 return PTR_ERR(dmc->base_drexi0);