Lines Matching refs:state
298 static u16 MXL_GetMasterControl(u8 *MasterReg, int state);
339 struct mxl5005s_state *state = fe->tuner_priv;
354 ByteTable[0] |= state->config->AgcMasterByte;
371 state->config->AgcMasterByte;
387 state->config->AgcMasterByte ;
404 struct mxl5005s_state *state = fe->tuner_priv;
405 state->TunerRegs_Num = TUNER_REGS_NUM ;
407 state->TunerRegs[0].Reg_Num = 9 ;
408 state->TunerRegs[0].Reg_Val = 0x40 ;
410 state->TunerRegs[1].Reg_Num = 11 ;
411 state->TunerRegs[1].Reg_Val = 0x19 ;
413 state->TunerRegs[2].Reg_Num = 12 ;
414 state->TunerRegs[2].Reg_Val = 0x60 ;
416 state->TunerRegs[3].Reg_Num = 13 ;
417 state->TunerRegs[3].Reg_Val = 0x00 ;
419 state->TunerRegs[4].Reg_Num = 14 ;
420 state->TunerRegs[4].Reg_Val = 0x00 ;
422 state->TunerRegs[5].Reg_Num = 15 ;
423 state->TunerRegs[5].Reg_Val = 0xC0 ;
425 state->TunerRegs[6].Reg_Num = 16 ;
426 state->TunerRegs[6].Reg_Val = 0x00 ;
428 state->TunerRegs[7].Reg_Num = 17 ;
429 state->TunerRegs[7].Reg_Val = 0x00 ;
431 state->TunerRegs[8].Reg_Num = 18 ;
432 state->TunerRegs[8].Reg_Val = 0x00 ;
434 state->TunerRegs[9].Reg_Num = 19 ;
435 state->TunerRegs[9].Reg_Val = 0x34 ;
437 state->TunerRegs[10].Reg_Num = 21 ;
438 state->TunerRegs[10].Reg_Val = 0x00 ;
440 state->TunerRegs[11].Reg_Num = 22 ;
441 state->TunerRegs[11].Reg_Val = 0x6B ;
443 state->TunerRegs[12].Reg_Num = 23 ;
444 state->TunerRegs[12].Reg_Val = 0x35 ;
446 state->TunerRegs[13].Reg_Num = 24 ;
447 state->TunerRegs[13].Reg_Val = 0x70 ;
449 state->TunerRegs[14].Reg_Num = 25 ;
450 state->TunerRegs[14].Reg_Val = 0x3E ;
452 state->TunerRegs[15].Reg_Num = 26 ;
453 state->TunerRegs[15].Reg_Val = 0x82 ;
455 state->TunerRegs[16].Reg_Num = 31 ;
456 state->TunerRegs[16].Reg_Val = 0x00 ;
458 state->TunerRegs[17].Reg_Num = 32 ;
459 state->TunerRegs[17].Reg_Val = 0x40 ;
461 state->TunerRegs[18].Reg_Num = 33 ;
462 state->TunerRegs[18].Reg_Val = 0x53 ;
464 state->TunerRegs[19].Reg_Num = 34 ;
465 state->TunerRegs[19].Reg_Val = 0x81 ;
467 state->TunerRegs[20].Reg_Num = 35 ;
468 state->TunerRegs[20].Reg_Val = 0xC9 ;
470 state->TunerRegs[21].Reg_Num = 36 ;
471 state->TunerRegs[21].Reg_Val = 0x01 ;
473 state->TunerRegs[22].Reg_Num = 37 ;
474 state->TunerRegs[22].Reg_Val = 0x00 ;
476 state->TunerRegs[23].Reg_Num = 41 ;
477 state->TunerRegs[23].Reg_Val = 0x00 ;
479 state->TunerRegs[24].Reg_Num = 42 ;
480 state->TunerRegs[24].Reg_Val = 0xF8 ;
482 state->TunerRegs[25].Reg_Num = 43 ;
483 state->TunerRegs[25].Reg_Val = 0x43 ;
485 state->TunerRegs[26].Reg_Num = 44 ;
486 state->TunerRegs[26].Reg_Val = 0x20 ;
488 state->TunerRegs[27].Reg_Num = 45 ;
489 state->TunerRegs[27].Reg_Val = 0x80 ;
491 state->TunerRegs[28].Reg_Num = 46 ;
492 state->TunerRegs[28].Reg_Val = 0x88 ;
494 state->TunerRegs[29].Reg_Num = 47 ;
495 state->TunerRegs[29].Reg_Val = 0x86 ;
497 state->TunerRegs[30].Reg_Num = 48 ;
498 state->TunerRegs[30].Reg_Val = 0x00 ;
500 state->TunerRegs[31].Reg_Num = 49 ;
501 state->TunerRegs[31].Reg_Val = 0x00 ;
503 state->TunerRegs[32].Reg_Num = 53 ;
504 state->TunerRegs[32].Reg_Val = 0x94 ;
506 state->TunerRegs[33].Reg_Num = 54 ;
507 state->TunerRegs[33].Reg_Val = 0xFA ;
509 state->TunerRegs[34].Reg_Num = 55 ;
510 state->TunerRegs[34].Reg_Val = 0x92 ;
512 state->TunerRegs[35].Reg_Num = 56 ;
513 state->TunerRegs[35].Reg_Val = 0x80 ;
515 state->TunerRegs[36].Reg_Num = 57 ;
516 state->TunerRegs[36].Reg_Val = 0x41 ;
518 state->TunerRegs[37].Reg_Num = 58 ;
519 state->TunerRegs[37].Reg_Val = 0xDB ;
521 state->TunerRegs[38].Reg_Num = 59 ;
522 state->TunerRegs[38].Reg_Val = 0x00 ;
524 state->TunerRegs[39].Reg_Num = 60 ;
525 state->TunerRegs[39].Reg_Val = 0x00 ;
527 state->TunerRegs[40].Reg_Num = 61 ;
528 state->TunerRegs[40].Reg_Val = 0x00 ;
530 state->TunerRegs[41].Reg_Num = 62 ;
531 state->TunerRegs[41].Reg_Val = 0x00 ;
533 state->TunerRegs[42].Reg_Num = 65 ;
534 state->TunerRegs[42].Reg_Val = 0xF8 ;
536 state->TunerRegs[43].Reg_Num = 66 ;
537 state->TunerRegs[43].Reg_Val = 0xE4 ;
539 state->TunerRegs[44].Reg_Num = 67 ;
540 state->TunerRegs[44].Reg_Val = 0x90 ;
542 state->TunerRegs[45].Reg_Num = 68 ;
543 state->TunerRegs[45].Reg_Val = 0xC0 ;
545 state->TunerRegs[46].Reg_Num = 69 ;
546 state->TunerRegs[46].Reg_Val = 0x01 ;
548 state->TunerRegs[47].Reg_Num = 70 ;
549 state->TunerRegs[47].Reg_Val = 0x50 ;
551 state->TunerRegs[48].Reg_Num = 71 ;
552 state->TunerRegs[48].Reg_Val = 0x06 ;
554 state->TunerRegs[49].Reg_Num = 72 ;
555 state->TunerRegs[49].Reg_Val = 0x00 ;
557 state->TunerRegs[50].Reg_Num = 73 ;
558 state->TunerRegs[50].Reg_Val = 0x20 ;
560 state->TunerRegs[51].Reg_Num = 76 ;
561 state->TunerRegs[51].Reg_Val = 0xBB ;
563 state->TunerRegs[52].Reg_Num = 77 ;
564 state->TunerRegs[52].Reg_Val = 0x13 ;
566 state->TunerRegs[53].Reg_Num = 81 ;
567 state->TunerRegs[53].Reg_Val = 0x04 ;
569 state->TunerRegs[54].Reg_Num = 82 ;
570 state->TunerRegs[54].Reg_Val = 0x75 ;
572 state->TunerRegs[55].Reg_Num = 83 ;
573 state->TunerRegs[55].Reg_Val = 0x00 ;
575 state->TunerRegs[56].Reg_Num = 84 ;
576 state->TunerRegs[56].Reg_Val = 0x00 ;
578 state->TunerRegs[57].Reg_Num = 85 ;
579 state->TunerRegs[57].Reg_Val = 0x00 ;
581 state->TunerRegs[58].Reg_Num = 91 ;
582 state->TunerRegs[58].Reg_Val = 0x70 ;
584 state->TunerRegs[59].Reg_Num = 92 ;
585 state->TunerRegs[59].Reg_Val = 0x00 ;
587 state->TunerRegs[60].Reg_Num = 93 ;
588 state->TunerRegs[60].Reg_Val = 0x00 ;
590 state->TunerRegs[61].Reg_Num = 94 ;
591 state->TunerRegs[61].Reg_Val = 0x00 ;
593 state->TunerRegs[62].Reg_Num = 95 ;
594 state->TunerRegs[62].Reg_Val = 0x0C ;
596 state->TunerRegs[63].Reg_Num = 96 ;
597 state->TunerRegs[63].Reg_Val = 0x00 ;
599 state->TunerRegs[64].Reg_Num = 97 ;
600 state->TunerRegs[64].Reg_Val = 0x00 ;
602 state->TunerRegs[65].Reg_Num = 98 ;
603 state->TunerRegs[65].Reg_Val = 0xE2 ;
605 state->TunerRegs[66].Reg_Num = 99 ;
606 state->TunerRegs[66].Reg_Val = 0x00 ;
608 state->TunerRegs[67].Reg_Num = 100 ;
609 state->TunerRegs[67].Reg_Val = 0x00 ;
611 state->TunerRegs[68].Reg_Num = 101 ;
612 state->TunerRegs[68].Reg_Val = 0x12 ;
614 state->TunerRegs[69].Reg_Num = 102 ;
615 state->TunerRegs[69].Reg_Val = 0x80 ;
617 state->TunerRegs[70].Reg_Num = 103 ;
618 state->TunerRegs[70].Reg_Val = 0x32 ;
620 state->TunerRegs[71].Reg_Num = 104 ;
621 state->TunerRegs[71].Reg_Val = 0xB4 ;
623 state->TunerRegs[72].Reg_Num = 105 ;
624 state->TunerRegs[72].Reg_Val = 0x60 ;
626 state->TunerRegs[73].Reg_Num = 106 ;
627 state->TunerRegs[73].Reg_Val = 0x83 ;
629 state->TunerRegs[74].Reg_Num = 107 ;
630 state->TunerRegs[74].Reg_Val = 0x84 ;
632 state->TunerRegs[75].Reg_Num = 108 ;
633 state->TunerRegs[75].Reg_Val = 0x9C ;
635 state->TunerRegs[76].Reg_Num = 109 ;
636 state->TunerRegs[76].Reg_Val = 0x02 ;
638 state->TunerRegs[77].Reg_Num = 110 ;
639 state->TunerRegs[77].Reg_Val = 0x81 ;
641 state->TunerRegs[78].Reg_Num = 111 ;
642 state->TunerRegs[78].Reg_Val = 0xC0 ;
644 state->TunerRegs[79].Reg_Num = 112 ;
645 state->TunerRegs[79].Reg_Val = 0x10 ;
647 state->TunerRegs[80].Reg_Num = 131 ;
648 state->TunerRegs[80].Reg_Val = 0x8A ;
650 state->TunerRegs[81].Reg_Num = 132 ;
651 state->TunerRegs[81].Reg_Val = 0x10 ;
653 state->TunerRegs[82].Reg_Num = 133 ;
654 state->TunerRegs[82].Reg_Val = 0x24 ;
656 state->TunerRegs[83].Reg_Num = 134 ;
657 state->TunerRegs[83].Reg_Val = 0x00 ;
659 state->TunerRegs[84].Reg_Num = 135 ;
660 state->TunerRegs[84].Reg_Val = 0x00 ;
662 state->TunerRegs[85].Reg_Num = 136 ;
663 state->TunerRegs[85].Reg_Val = 0x7E ;
665 state->TunerRegs[86].Reg_Num = 137 ;
666 state->TunerRegs[86].Reg_Val = 0x40 ;
668 state->TunerRegs[87].Reg_Num = 138 ;
669 state->TunerRegs[87].Reg_Val = 0x38 ;
671 state->TunerRegs[88].Reg_Num = 146 ;
672 state->TunerRegs[88].Reg_Val = 0xF6 ;
674 state->TunerRegs[89].Reg_Num = 147 ;
675 state->TunerRegs[89].Reg_Val = 0x1A ;
677 state->TunerRegs[90].Reg_Num = 148 ;
678 state->TunerRegs[90].Reg_Val = 0x62 ;
680 state->TunerRegs[91].Reg_Num = 149 ;
681 state->TunerRegs[91].Reg_Val = 0x33 ;
683 state->TunerRegs[92].Reg_Num = 150 ;
684 state->TunerRegs[92].Reg_Val = 0x80 ;
686 state->TunerRegs[93].Reg_Num = 156 ;
687 state->TunerRegs[93].Reg_Val = 0x56 ;
689 state->TunerRegs[94].Reg_Num = 157 ;
690 state->TunerRegs[94].Reg_Val = 0x17 ;
692 state->TunerRegs[95].Reg_Num = 158 ;
693 state->TunerRegs[95].Reg_Val = 0xA9 ;
695 state->TunerRegs[96].Reg_Num = 159 ;
696 state->TunerRegs[96].Reg_Val = 0x00 ;
698 state->TunerRegs[97].Reg_Num = 160 ;
699 state->TunerRegs[97].Reg_Val = 0x00 ;
701 state->TunerRegs[98].Reg_Num = 161 ;
702 state->TunerRegs[98].Reg_Val = 0x00 ;
704 state->TunerRegs[99].Reg_Num = 162 ;
705 state->TunerRegs[99].Reg_Val = 0x40 ;
707 state->TunerRegs[100].Reg_Num = 166 ;
708 state->TunerRegs[100].Reg_Val = 0xAE ;
710 state->TunerRegs[101].Reg_Num = 167 ;
711 state->TunerRegs[101].Reg_Val = 0x1B ;
713 state->TunerRegs[102].Reg_Num = 168 ;
714 state->TunerRegs[102].Reg_Val = 0xF2 ;
716 state->TunerRegs[103].Reg_Num = 195 ;
717 state->TunerRegs[103].Reg_Val = 0x00 ;
724 struct mxl5005s_state *state = fe->tuner_priv;
725 state->Init_Ctrl_Num = INITCTRL_NUM;
727 state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ;
728 state->Init_Ctrl[0].size = 1 ;
729 state->Init_Ctrl[0].addr[0] = 73;
730 state->Init_Ctrl[0].bit[0] = 7;
731 state->Init_Ctrl[0].val[0] = 0;
733 state->Init_Ctrl[1].Ctrl_Num = BB_MODE ;
734 state->Init_Ctrl[1].size = 1 ;
735 state->Init_Ctrl[1].addr[0] = 53;
736 state->Init_Ctrl[1].bit[0] = 2;
737 state->Init_Ctrl[1].val[0] = 1;
739 state->Init_Ctrl[2].Ctrl_Num = BB_BUF ;
740 state->Init_Ctrl[2].size = 2 ;
741 state->Init_Ctrl[2].addr[0] = 53;
742 state->Init_Ctrl[2].bit[0] = 1;
743 state->Init_Ctrl[2].val[0] = 0;
744 state->Init_Ctrl[2].addr[1] = 57;
745 state->Init_Ctrl[2].bit[1] = 0;
746 state->Init_Ctrl[2].val[1] = 1;
748 state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ;
749 state->Init_Ctrl[3].size = 1 ;
750 state->Init_Ctrl[3].addr[0] = 53;
751 state->Init_Ctrl[3].bit[0] = 0;
752 state->Init_Ctrl[3].val[0] = 0;
754 state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ;
755 state->Init_Ctrl[4].size = 3 ;
756 state->Init_Ctrl[4].addr[0] = 53;
757 state->Init_Ctrl[4].bit[0] = 5;
758 state->Init_Ctrl[4].val[0] = 0;
759 state->Init_Ctrl[4].addr[1] = 53;
760 state->Init_Ctrl[4].bit[1] = 6;
761 state->Init_Ctrl[4].val[1] = 0;
762 state->Init_Ctrl[4].addr[2] = 53;
763 state->Init_Ctrl[4].bit[2] = 7;
764 state->Init_Ctrl[4].val[2] = 1;
766 state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ;
767 state->Init_Ctrl[5].size = 1 ;
768 state->Init_Ctrl[5].addr[0] = 59;
769 state->Init_Ctrl[5].bit[0] = 0;
770 state->Init_Ctrl[5].val[0] = 0;
772 state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ;
773 state->Init_Ctrl[6].size = 2 ;
774 state->Init_Ctrl[6].addr[0] = 53;
775 state->Init_Ctrl[6].bit[0] = 3;
776 state->Init_Ctrl[6].val[0] = 0;
777 state->Init_Ctrl[6].addr[1] = 53;
778 state->Init_Ctrl[6].bit[1] = 4;
779 state->Init_Ctrl[6].val[1] = 1;
781 state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ;
782 state->Init_Ctrl[7].size = 4 ;
783 state->Init_Ctrl[7].addr[0] = 22;
784 state->Init_Ctrl[7].bit[0] = 4;
785 state->Init_Ctrl[7].val[0] = 0;
786 state->Init_Ctrl[7].addr[1] = 22;
787 state->Init_Ctrl[7].bit[1] = 5;
788 state->Init_Ctrl[7].val[1] = 1;
789 state->Init_Ctrl[7].addr[2] = 22;
790 state->Init_Ctrl[7].bit[2] = 6;
791 state->Init_Ctrl[7].val[2] = 1;
792 state->Init_Ctrl[7].addr[3] = 22;
793 state->Init_Ctrl[7].bit[3] = 7;
794 state->Init_Ctrl[7].val[3] = 0;
796 state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ;
797 state->Init_Ctrl[8].size = 1 ;
798 state->Init_Ctrl[8].addr[0] = 22;
799 state->Init_Ctrl[8].bit[0] = 2;
800 state->Init_Ctrl[8].val[0] = 0;
802 state->Init_Ctrl[9].Ctrl_Num = AGC_IF ;
803 state->Init_Ctrl[9].size = 4 ;
804 state->Init_Ctrl[9].addr[0] = 76;
805 state->Init_Ctrl[9].bit[0] = 0;
806 state->Init_Ctrl[9].val[0] = 1;
807 state->Init_Ctrl[9].addr[1] = 76;
808 state->Init_Ctrl[9].bit[1] = 1;
809 state->Init_Ctrl[9].val[1] = 1;
810 state->Init_Ctrl[9].addr[2] = 76;
811 state->Init_Ctrl[9].bit[2] = 2;
812 state->Init_Ctrl[9].val[2] = 0;
813 state->Init_Ctrl[9].addr[3] = 76;
814 state->Init_Ctrl[9].bit[3] = 3;
815 state->Init_Ctrl[9].val[3] = 1;
817 state->Init_Ctrl[10].Ctrl_Num = AGC_RF ;
818 state->Init_Ctrl[10].size = 4 ;
819 state->Init_Ctrl[10].addr[0] = 76;
820 state->Init_Ctrl[10].bit[0] = 4;
821 state->Init_Ctrl[10].val[0] = 1;
822 state->Init_Ctrl[10].addr[1] = 76;
823 state->Init_Ctrl[10].bit[1] = 5;
824 state->Init_Ctrl[10].val[1] = 1;
825 state->Init_Ctrl[10].addr[2] = 76;
826 state->Init_Ctrl[10].bit[2] = 6;
827 state->Init_Ctrl[10].val[2] = 0;
828 state->Init_Ctrl[10].addr[3] = 76;
829 state->Init_Ctrl[10].bit[3] = 7;
830 state->Init_Ctrl[10].val[3] = 1;
832 state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ;
833 state->Init_Ctrl[11].size = 5 ;
834 state->Init_Ctrl[11].addr[0] = 43;
835 state->Init_Ctrl[11].bit[0] = 3;
836 state->Init_Ctrl[11].val[0] = 0;
837 state->Init_Ctrl[11].addr[1] = 43;
838 state->Init_Ctrl[11].bit[1] = 4;
839 state->Init_Ctrl[11].val[1] = 0;
840 state->Init_Ctrl[11].addr[2] = 43;
841 state->Init_Ctrl[11].bit[2] = 5;
842 state->Init_Ctrl[11].val[2] = 0;
843 state->Init_Ctrl[11].addr[3] = 43;
844 state->Init_Ctrl[11].bit[3] = 6;
845 state->Init_Ctrl[11].val[3] = 1;
846 state->Init_Ctrl[11].addr[4] = 43;
847 state->Init_Ctrl[11].bit[4] = 7;
848 state->Init_Ctrl[11].val[4] = 0;
850 state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ;
851 state->Init_Ctrl[12].size = 6 ;
852 state->Init_Ctrl[12].addr[0] = 44;
853 state->Init_Ctrl[12].bit[0] = 2;
854 state->Init_Ctrl[12].val[0] = 0;
855 state->Init_Ctrl[12].addr[1] = 44;
856 state->Init_Ctrl[12].bit[1] = 3;
857 state->Init_Ctrl[12].val[1] = 0;
858 state->Init_Ctrl[12].addr[2] = 44;
859 state->Init_Ctrl[12].bit[2] = 4;
860 state->Init_Ctrl[12].val[2] = 0;
861 state->Init_Ctrl[12].addr[3] = 44;
862 state->Init_Ctrl[12].bit[3] = 5;
863 state->Init_Ctrl[12].val[3] = 1;
864 state->Init_Ctrl[12].addr[4] = 44;
865 state->Init_Ctrl[12].bit[4] = 6;
866 state->Init_Ctrl[12].val[4] = 0;
867 state->Init_Ctrl[12].addr[5] = 44;
868 state->Init_Ctrl[12].bit[5] = 7;
869 state->Init_Ctrl[12].val[5] = 0;
871 state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ;
872 state->Init_Ctrl[13].size = 7 ;
873 state->Init_Ctrl[13].addr[0] = 11;
874 state->Init_Ctrl[13].bit[0] = 0;
875 state->Init_Ctrl[13].val[0] = 1;
876 state->Init_Ctrl[13].addr[1] = 11;
877 state->Init_Ctrl[13].bit[1] = 1;
878 state->Init_Ctrl[13].val[1] = 0;
879 state->Init_Ctrl[13].addr[2] = 11;
880 state->Init_Ctrl[13].bit[2] = 2;
881 state->Init_Ctrl[13].val[2] = 0;
882 state->Init_Ctrl[13].addr[3] = 11;
883 state->Init_Ctrl[13].bit[3] = 3;
884 state->Init_Ctrl[13].val[3] = 1;
885 state->Init_Ctrl[13].addr[4] = 11;
886 state->Init_Ctrl[13].bit[4] = 4;
887 state->Init_Ctrl[13].val[4] = 1;
888 state->Init_Ctrl[13].addr[5] = 11;
889 state->Init_Ctrl[13].bit[5] = 5;
890 state->Init_Ctrl[13].val[5] = 0;
891 state->Init_Ctrl[13].addr[6] = 11;
892 state->Init_Ctrl[13].bit[6] = 6;
893 state->Init_Ctrl[13].val[6] = 0;
895 state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ;
896 state->Init_Ctrl[14].size = 16 ;
897 state->Init_Ctrl[14].addr[0] = 13;
898 state->Init_Ctrl[14].bit[0] = 0;
899 state->Init_Ctrl[14].val[0] = 0;
900 state->Init_Ctrl[14].addr[1] = 13;
901 state->Init_Ctrl[14].bit[1] = 1;
902 state->Init_Ctrl[14].val[1] = 0;
903 state->Init_Ctrl[14].addr[2] = 13;
904 state->Init_Ctrl[14].bit[2] = 2;
905 state->Init_Ctrl[14].val[2] = 0;
906 state->Init_Ctrl[14].addr[3] = 13;
907 state->Init_Ctrl[14].bit[3] = 3;
908 state->Init_Ctrl[14].val[3] = 0;
909 state->Init_Ctrl[14].addr[4] = 13;
910 state->Init_Ctrl[14].bit[4] = 4;
911 state->Init_Ctrl[14].val[4] = 0;
912 state->Init_Ctrl[14].addr[5] = 13;
913 state->Init_Ctrl[14].bit[5] = 5;
914 state->Init_Ctrl[14].val[5] = 0;
915 state->Init_Ctrl[14].addr[6] = 13;
916 state->Init_Ctrl[14].bit[6] = 6;
917 state->Init_Ctrl[14].val[6] = 0;
918 state->Init_Ctrl[14].addr[7] = 13;
919 state->Init_Ctrl[14].bit[7] = 7;
920 state->Init_Ctrl[14].val[7] = 0;
921 state->Init_Ctrl[14].addr[8] = 12;
922 state->Init_Ctrl[14].bit[8] = 0;
923 state->Init_Ctrl[14].val[8] = 0;
924 state->Init_Ctrl[14].addr[9] = 12;
925 state->Init_Ctrl[14].bit[9] = 1;
926 state->Init_Ctrl[14].val[9] = 0;
927 state->Init_Ctrl[14].addr[10] = 12;
928 state->Init_Ctrl[14].bit[10] = 2;
929 state->Init_Ctrl[14].val[10] = 0;
930 state->Init_Ctrl[14].addr[11] = 12;
931 state->Init_Ctrl[14].bit[11] = 3;
932 state->Init_Ctrl[14].val[11] = 0;
933 state->Init_Ctrl[14].addr[12] = 12;
934 state->Init_Ctrl[14].bit[12] = 4;
935 state->Init_Ctrl[14].val[12] = 0;
936 state->Init_Ctrl[14].addr[13] = 12;
937 state->Init_Ctrl[14].bit[13] = 5;
938 state->Init_Ctrl[14].val[13] = 1;
939 state->Init_Ctrl[14].addr[14] = 12;
940 state->Init_Ctrl[14].bit[14] = 6;
941 state->Init_Ctrl[14].val[14] = 1;
942 state->Init_Ctrl[14].addr[15] = 12;
943 state->Init_Ctrl[14].bit[15] = 7;
944 state->Init_Ctrl[14].val[15] = 0;
946 state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ;
947 state->Init_Ctrl[15].size = 3 ;
948 state->Init_Ctrl[15].addr[0] = 147;
949 state->Init_Ctrl[15].bit[0] = 2;
950 state->Init_Ctrl[15].val[0] = 0;
951 state->Init_Ctrl[15].addr[1] = 147;
952 state->Init_Ctrl[15].bit[1] = 3;
953 state->Init_Ctrl[15].val[1] = 1;
954 state->Init_Ctrl[15].addr[2] = 147;
955 state->Init_Ctrl[15].bit[2] = 4;
956 state->Init_Ctrl[15].val[2] = 1;
958 state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ;
959 state->Init_Ctrl[16].size = 2 ;
960 state->Init_Ctrl[16].addr[0] = 147;
961 state->Init_Ctrl[16].bit[0] = 0;
962 state->Init_Ctrl[16].val[0] = 0;
963 state->Init_Ctrl[16].addr[1] = 147;
964 state->Init_Ctrl[16].bit[1] = 1;
965 state->Init_Ctrl[16].val[1] = 1;
967 state->Init_Ctrl[17].Ctrl_Num = EN_AAF ;
968 state->Init_Ctrl[17].size = 1 ;
969 state->Init_Ctrl[17].addr[0] = 147;
970 state->Init_Ctrl[17].bit[0] = 7;
971 state->Init_Ctrl[17].val[0] = 0;
973 state->Init_Ctrl[18].Ctrl_Num = EN_3P ;
974 state->Init_Ctrl[18].size = 1 ;
975 state->Init_Ctrl[18].addr[0] = 147;
976 state->Init_Ctrl[18].bit[0] = 6;
977 state->Init_Ctrl[18].val[0] = 0;
979 state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ;
980 state->Init_Ctrl[19].size = 1 ;
981 state->Init_Ctrl[19].addr[0] = 156;
982 state->Init_Ctrl[19].bit[0] = 0;
983 state->Init_Ctrl[19].val[0] = 0;
985 state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ;
986 state->Init_Ctrl[20].size = 1 ;
987 state->Init_Ctrl[20].addr[0] = 147;
988 state->Init_Ctrl[20].bit[0] = 5;
989 state->Init_Ctrl[20].val[0] = 0;
991 state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ;
992 state->Init_Ctrl[21].size = 1 ;
993 state->Init_Ctrl[21].addr[0] = 137;
994 state->Init_Ctrl[21].bit[0] = 4;
995 state->Init_Ctrl[21].val[0] = 0;
997 state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ;
998 state->Init_Ctrl[22].size = 1 ;
999 state->Init_Ctrl[22].addr[0] = 137;
1000 state->Init_Ctrl[22].bit[0] = 7;
1001 state->Init_Ctrl[22].val[0] = 0;
1003 state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ;
1004 state->Init_Ctrl[23].size = 1 ;
1005 state->Init_Ctrl[23].addr[0] = 91;
1006 state->Init_Ctrl[23].bit[0] = 5;
1007 state->Init_Ctrl[23].val[0] = 1;
1009 state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ;
1010 state->Init_Ctrl[24].size = 1 ;
1011 state->Init_Ctrl[24].addr[0] = 43;
1012 state->Init_Ctrl[24].bit[0] = 0;
1013 state->Init_Ctrl[24].val[0] = 1;
1015 state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ;
1016 state->Init_Ctrl[25].size = 2 ;
1017 state->Init_Ctrl[25].addr[0] = 22;
1018 state->Init_Ctrl[25].bit[0] = 0;
1019 state->Init_Ctrl[25].val[0] = 1;
1020 state->Init_Ctrl[25].addr[1] = 22;
1021 state->Init_Ctrl[25].bit[1] = 1;
1022 state->Init_Ctrl[25].val[1] = 1;
1024 state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ;
1025 state->Init_Ctrl[26].size = 1 ;
1026 state->Init_Ctrl[26].addr[0] = 134;
1027 state->Init_Ctrl[26].bit[0] = 2;
1028 state->Init_Ctrl[26].val[0] = 0;
1030 state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ;
1031 state->Init_Ctrl[27].size = 1 ;
1032 state->Init_Ctrl[27].addr[0] = 137;
1033 state->Init_Ctrl[27].bit[0] = 3;
1034 state->Init_Ctrl[27].val[0] = 0;
1036 state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ;
1037 state->Init_Ctrl[28].size = 1 ;
1038 state->Init_Ctrl[28].addr[0] = 77;
1039 state->Init_Ctrl[28].bit[0] = 7;
1040 state->Init_Ctrl[28].val[0] = 0;
1042 state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ;
1043 state->Init_Ctrl[29].size = 1 ;
1044 state->Init_Ctrl[29].addr[0] = 166;
1045 state->Init_Ctrl[29].bit[0] = 7;
1046 state->Init_Ctrl[29].val[0] = 1;
1048 state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ;
1049 state->Init_Ctrl[30].size = 3 ;
1050 state->Init_Ctrl[30].addr[0] = 166;
1051 state->Init_Ctrl[30].bit[0] = 0;
1052 state->Init_Ctrl[30].val[0] = 0;
1053 state->Init_Ctrl[30].addr[1] = 166;
1054 state->Init_Ctrl[30].bit[1] = 1;
1055 state->Init_Ctrl[30].val[1] = 1;
1056 state->Init_Ctrl[30].addr[2] = 166;
1057 state->Init_Ctrl[30].bit[2] = 2;
1058 state->Init_Ctrl[30].val[2] = 1;
1060 state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ;
1061 state->Init_Ctrl[31].size = 3 ;
1062 state->Init_Ctrl[31].addr[0] = 166;
1063 state->Init_Ctrl[31].bit[0] = 3;
1064 state->Init_Ctrl[31].val[0] = 1;
1065 state->Init_Ctrl[31].addr[1] = 166;
1066 state->Init_Ctrl[31].bit[1] = 4;
1067 state->Init_Ctrl[31].val[1] = 0;
1068 state->Init_Ctrl[31].addr[2] = 166;
1069 state->Init_Ctrl[31].bit[2] = 5;
1070 state->Init_Ctrl[31].val[2] = 1;
1072 state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ;
1073 state->Init_Ctrl[32].size = 3 ;
1074 state->Init_Ctrl[32].addr[0] = 167;
1075 state->Init_Ctrl[32].bit[0] = 0;
1076 state->Init_Ctrl[32].val[0] = 1;
1077 state->Init_Ctrl[32].addr[1] = 167;
1078 state->Init_Ctrl[32].bit[1] = 1;
1079 state->Init_Ctrl[32].val[1] = 1;
1080 state->Init_Ctrl[32].addr[2] = 167;
1081 state->Init_Ctrl[32].bit[2] = 2;
1082 state->Init_Ctrl[32].val[2] = 0;
1084 state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ;
1085 state->Init_Ctrl[33].size = 4 ;
1086 state->Init_Ctrl[33].addr[0] = 168;
1087 state->Init_Ctrl[33].bit[0] = 0;
1088 state->Init_Ctrl[33].val[0] = 0;
1089 state->Init_Ctrl[33].addr[1] = 168;
1090 state->Init_Ctrl[33].bit[1] = 1;
1091 state->Init_Ctrl[33].val[1] = 1;
1092 state->Init_Ctrl[33].addr[2] = 168;
1093 state->Init_Ctrl[33].bit[2] = 2;
1094 state->Init_Ctrl[33].val[2] = 0;
1095 state->Init_Ctrl[33].addr[3] = 168;
1096 state->Init_Ctrl[33].bit[3] = 3;
1097 state->Init_Ctrl[33].val[3] = 0;
1099 state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ;
1100 state->Init_Ctrl[34].size = 4 ;
1101 state->Init_Ctrl[34].addr[0] = 168;
1102 state->Init_Ctrl[34].bit[0] = 4;
1103 state->Init_Ctrl[34].val[0] = 1;
1104 state->Init_Ctrl[34].addr[1] = 168;
1105 state->Init_Ctrl[34].bit[1] = 5;
1106 state->Init_Ctrl[34].val[1] = 1;
1107 state->Init_Ctrl[34].addr[2] = 168;
1108 state->Init_Ctrl[34].bit[2] = 6;
1109 state->Init_Ctrl[34].val[2] = 1;
1110 state->Init_Ctrl[34].addr[3] = 168;
1111 state->Init_Ctrl[34].bit[3] = 7;
1112 state->Init_Ctrl[34].val[3] = 1;
1114 state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ;
1115 state->Init_Ctrl[35].size = 1 ;
1116 state->Init_Ctrl[35].addr[0] = 135;
1117 state->Init_Ctrl[35].bit[0] = 0;
1118 state->Init_Ctrl[35].val[0] = 0;
1120 state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ;
1121 state->Init_Ctrl[36].size = 1 ;
1122 state->Init_Ctrl[36].addr[0] = 56;
1123 state->Init_Ctrl[36].bit[0] = 3;
1124 state->Init_Ctrl[36].val[0] = 0;
1126 state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ;
1127 state->Init_Ctrl[37].size = 7 ;
1128 state->Init_Ctrl[37].addr[0] = 59;
1129 state->Init_Ctrl[37].bit[0] = 1;
1130 state->Init_Ctrl[37].val[0] = 0;
1131 state->Init_Ctrl[37].addr[1] = 59;
1132 state->Init_Ctrl[37].bit[1] = 2;
1133 state->Init_Ctrl[37].val[1] = 0;
1134 state->Init_Ctrl[37].addr[2] = 59;
1135 state->Init_Ctrl[37].bit[2] = 3;
1136 state->Init_Ctrl[37].val[2] = 0;
1137 state->Init_Ctrl[37].addr[3] = 59;
1138 state->Init_Ctrl[37].bit[3] = 4;
1139 state->Init_Ctrl[37].val[3] = 0;
1140 state->Init_Ctrl[37].addr[4] = 59;
1141 state->Init_Ctrl[37].bit[4] = 5;
1142 state->Init_Ctrl[37].val[4] = 0;
1143 state->Init_Ctrl[37].addr[5] = 59;
1144 state->Init_Ctrl[37].bit[5] = 6;
1145 state->Init_Ctrl[37].val[5] = 0;
1146 state->Init_Ctrl[37].addr[6] = 59;
1147 state->Init_Ctrl[37].bit[6] = 7;
1148 state->Init_Ctrl[37].val[6] = 0;
1150 state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ;
1151 state->Init_Ctrl[38].size = 6 ;
1152 state->Init_Ctrl[38].addr[0] = 32;
1153 state->Init_Ctrl[38].bit[0] = 2;
1154 state->Init_Ctrl[38].val[0] = 0;
1155 state->Init_Ctrl[38].addr[1] = 32;
1156 state->Init_Ctrl[38].bit[1] = 3;
1157 state->Init_Ctrl[38].val[1] = 0;
1158 state->Init_Ctrl[38].addr[2] = 32;
1159 state->Init_Ctrl[38].bit[2] = 4;
1160 state->Init_Ctrl[38].val[2] = 0;
1161 state->Init_Ctrl[38].addr[3] = 32;
1162 state->Init_Ctrl[38].bit[3] = 5;
1163 state->Init_Ctrl[38].val[3] = 0;
1164 state->Init_Ctrl[38].addr[4] = 32;
1165 state->Init_Ctrl[38].bit[4] = 6;
1166 state->Init_Ctrl[38].val[4] = 1;
1167 state->Init_Ctrl[38].addr[5] = 32;
1168 state->Init_Ctrl[38].bit[5] = 7;
1169 state->Init_Ctrl[38].val[5] = 0;
1171 state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ;
1172 state->Init_Ctrl[39].size = 1 ;
1173 state->Init_Ctrl[39].addr[0] = 25;
1174 state->Init_Ctrl[39].bit[0] = 3;
1175 state->Init_Ctrl[39].val[0] = 1;
1178 state->CH_Ctrl_Num = CHCTRL_NUM ;
1180 state->CH_Ctrl[0].Ctrl_Num = DN_POLY ;
1181 state->CH_Ctrl[0].size = 2 ;
1182 state->CH_Ctrl[0].addr[0] = 68;
1183 state->CH_Ctrl[0].bit[0] = 6;
1184 state->CH_Ctrl[0].val[0] = 1;
1185 state->CH_Ctrl[0].addr[1] = 68;
1186 state->CH_Ctrl[0].bit[1] = 7;
1187 state->CH_Ctrl[0].val[1] = 1;
1189 state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ;
1190 state->CH_Ctrl[1].size = 2 ;
1191 state->CH_Ctrl[1].addr[0] = 70;
1192 state->CH_Ctrl[1].bit[0] = 6;
1193 state->CH_Ctrl[1].val[0] = 1;
1194 state->CH_Ctrl[1].addr[1] = 70;
1195 state->CH_Ctrl[1].bit[1] = 7;
1196 state->CH_Ctrl[1].val[1] = 0;
1198 state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ;
1199 state->CH_Ctrl[2].size = 9 ;
1200 state->CH_Ctrl[2].addr[0] = 69;
1201 state->CH_Ctrl[2].bit[0] = 5;
1202 state->CH_Ctrl[2].val[0] = 0;
1203 state->CH_Ctrl[2].addr[1] = 69;
1204 state->CH_Ctrl[2].bit[1] = 6;
1205 state->CH_Ctrl[2].val[1] = 0;
1206 state->CH_Ctrl[2].addr[2] = 69;
1207 state->CH_Ctrl[2].bit[2] = 7;
1208 state->CH_Ctrl[2].val[2] = 0;
1209 state->CH_Ctrl[2].addr[3] = 68;
1210 state->CH_Ctrl[2].bit[3] = 0;
1211 state->CH_Ctrl[2].val[3] = 0;
1212 state->CH_Ctrl[2].addr[4] = 68;
1213 state->CH_Ctrl[2].bit[4] = 1;
1214 state->CH_Ctrl[2].val[4] = 0;
1215 state->CH_Ctrl[2].addr[5] = 68;
1216 state->CH_Ctrl[2].bit[5] = 2;
1217 state->CH_Ctrl[2].val[5] = 0;
1218 state->CH_Ctrl[2].addr[6] = 68;
1219 state->CH_Ctrl[2].bit[6] = 3;
1220 state->CH_Ctrl[2].val[6] = 0;
1221 state->CH_Ctrl[2].addr[7] = 68;
1222 state->CH_Ctrl[2].bit[7] = 4;
1223 state->CH_Ctrl[2].val[7] = 0;
1224 state->CH_Ctrl[2].addr[8] = 68;
1225 state->CH_Ctrl[2].bit[8] = 5;
1226 state->CH_Ctrl[2].val[8] = 0;
1228 state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ;
1229 state->CH_Ctrl[3].size = 1 ;
1230 state->CH_Ctrl[3].addr[0] = 70;
1231 state->CH_Ctrl[3].bit[0] = 5;
1232 state->CH_Ctrl[3].val[0] = 0;
1234 state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ;
1235 state->CH_Ctrl[4].size = 3 ;
1236 state->CH_Ctrl[4].addr[0] = 73;
1237 state->CH_Ctrl[4].bit[0] = 4;
1238 state->CH_Ctrl[4].val[0] = 0;
1239 state->CH_Ctrl[4].addr[1] = 73;
1240 state->CH_Ctrl[4].bit[1] = 5;
1241 state->CH_Ctrl[4].val[1] = 1;
1242 state->CH_Ctrl[4].addr[2] = 73;
1243 state->CH_Ctrl[4].bit[2] = 6;
1244 state->CH_Ctrl[4].val[2] = 0;
1246 state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ;
1247 state->CH_Ctrl[5].size = 4 ;
1248 state->CH_Ctrl[5].addr[0] = 70;
1249 state->CH_Ctrl[5].bit[0] = 0;
1250 state->CH_Ctrl[5].val[0] = 0;
1251 state->CH_Ctrl[5].addr[1] = 70;
1252 state->CH_Ctrl[5].bit[1] = 1;
1253 state->CH_Ctrl[5].val[1] = 0;
1254 state->CH_Ctrl[5].addr[2] = 70;
1255 state->CH_Ctrl[5].bit[2] = 2;
1256 state->CH_Ctrl[5].val[2] = 0;
1257 state->CH_Ctrl[5].addr[3] = 70;
1258 state->CH_Ctrl[5].bit[3] = 3;
1259 state->CH_Ctrl[5].val[3] = 0;
1261 state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ;
1262 state->CH_Ctrl[6].size = 1 ;
1263 state->CH_Ctrl[6].addr[0] = 70;
1264 state->CH_Ctrl[6].bit[0] = 4;
1265 state->CH_Ctrl[6].val[0] = 1;
1267 state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ;
1268 state->CH_Ctrl[7].size = 1 ;
1269 state->CH_Ctrl[7].addr[0] = 111;
1270 state->CH_Ctrl[7].bit[0] = 4;
1271 state->CH_Ctrl[7].val[0] = 0;
1273 state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ;
1274 state->CH_Ctrl[8].size = 1 ;
1275 state->CH_Ctrl[8].addr[0] = 111;
1276 state->CH_Ctrl[8].bit[0] = 7;
1277 state->CH_Ctrl[8].val[0] = 1;
1279 state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ;
1280 state->CH_Ctrl[9].size = 1 ;
1281 state->CH_Ctrl[9].addr[0] = 111;
1282 state->CH_Ctrl[9].bit[0] = 6;
1283 state->CH_Ctrl[9].val[0] = 1;
1285 state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ;
1286 state->CH_Ctrl[10].size = 1 ;
1287 state->CH_Ctrl[10].addr[0] = 111;
1288 state->CH_Ctrl[10].bit[0] = 5;
1289 state->CH_Ctrl[10].val[0] = 0;
1291 state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ;
1292 state->CH_Ctrl[11].size = 2 ;
1293 state->CH_Ctrl[11].addr[0] = 110;
1294 state->CH_Ctrl[11].bit[0] = 0;
1295 state->CH_Ctrl[11].val[0] = 1;
1296 state->CH_Ctrl[11].addr[1] = 110;
1297 state->CH_Ctrl[11].bit[1] = 1;
1298 state->CH_Ctrl[11].val[1] = 0;
1300 state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ;
1301 state->CH_Ctrl[12].size = 3 ;
1302 state->CH_Ctrl[12].addr[0] = 69;
1303 state->CH_Ctrl[12].bit[0] = 2;
1304 state->CH_Ctrl[12].val[0] = 0;
1305 state->CH_Ctrl[12].addr[1] = 69;
1306 state->CH_Ctrl[12].bit[1] = 3;
1307 state->CH_Ctrl[12].val[1] = 0;
1308 state->CH_Ctrl[12].addr[2] = 69;
1309 state->CH_Ctrl[12].bit[2] = 4;
1310 state->CH_Ctrl[12].val[2] = 0;
1312 state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ;
1313 state->CH_Ctrl[13].size = 6 ;
1314 state->CH_Ctrl[13].addr[0] = 110;
1315 state->CH_Ctrl[13].bit[0] = 2;
1316 state->CH_Ctrl[13].val[0] = 0;
1317 state->CH_Ctrl[13].addr[1] = 110;
1318 state->CH_Ctrl[13].bit[1] = 3;
1319 state->CH_Ctrl[13].val[1] = 0;
1320 state->CH_Ctrl[13].addr[2] = 110;
1321 state->CH_Ctrl[13].bit[2] = 4;
1322 state->CH_Ctrl[13].val[2] = 0;
1323 state->CH_Ctrl[13].addr[3] = 110;
1324 state->CH_Ctrl[13].bit[3] = 5;
1325 state->CH_Ctrl[13].val[3] = 0;
1326 state->CH_Ctrl[13].addr[4] = 110;
1327 state->CH_Ctrl[13].bit[4] = 6;
1328 state->CH_Ctrl[13].val[4] = 0;
1329 state->CH_Ctrl[13].addr[5] = 110;
1330 state->CH_Ctrl[13].bit[5] = 7;
1331 state->CH_Ctrl[13].val[5] = 1;
1333 state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ;
1334 state->CH_Ctrl[14].size = 7 ;
1335 state->CH_Ctrl[14].addr[0] = 14;
1336 state->CH_Ctrl[14].bit[0] = 0;
1337 state->CH_Ctrl[14].val[0] = 0;
1338 state->CH_Ctrl[14].addr[1] = 14;
1339 state->CH_Ctrl[14].bit[1] = 1;
1340 state->CH_Ctrl[14].val[1] = 0;
1341 state->CH_Ctrl[14].addr[2] = 14;
1342 state->CH_Ctrl[14].bit[2] = 2;
1343 state->CH_Ctrl[14].val[2] = 0;
1344 state->CH_Ctrl[14].addr[3] = 14;
1345 state->CH_Ctrl[14].bit[3] = 3;
1346 state->CH_Ctrl[14].val[3] = 0;
1347 state->CH_Ctrl[14].addr[4] = 14;
1348 state->CH_Ctrl[14].bit[4] = 4;
1349 state->CH_Ctrl[14].val[4] = 0;
1350 state->CH_Ctrl[14].addr[5] = 14;
1351 state->CH_Ctrl[14].bit[5] = 5;
1352 state->CH_Ctrl[14].val[5] = 0;
1353 state->CH_Ctrl[14].addr[6] = 14;
1354 state->CH_Ctrl[14].bit[6] = 6;
1355 state->CH_Ctrl[14].val[6] = 0;
1357 state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ;
1358 state->CH_Ctrl[15].size = 18 ;
1359 state->CH_Ctrl[15].addr[0] = 17;
1360 state->CH_Ctrl[15].bit[0] = 6;
1361 state->CH_Ctrl[15].val[0] = 0;
1362 state->CH_Ctrl[15].addr[1] = 17;
1363 state->CH_Ctrl[15].bit[1] = 7;
1364 state->CH_Ctrl[15].val[1] = 0;
1365 state->CH_Ctrl[15].addr[2] = 16;
1366 state->CH_Ctrl[15].bit[2] = 0;
1367 state->CH_Ctrl[15].val[2] = 0;
1368 state->CH_Ctrl[15].addr[3] = 16;
1369 state->CH_Ctrl[15].bit[3] = 1;
1370 state->CH_Ctrl[15].val[3] = 0;
1371 state->CH_Ctrl[15].addr[4] = 16;
1372 state->CH_Ctrl[15].bit[4] = 2;
1373 state->CH_Ctrl[15].val[4] = 0;
1374 state->CH_Ctrl[15].addr[5] = 16;
1375 state->CH_Ctrl[15].bit[5] = 3;
1376 state->CH_Ctrl[15].val[5] = 0;
1377 state->CH_Ctrl[15].addr[6] = 16;
1378 state->CH_Ctrl[15].bit[6] = 4;
1379 state->CH_Ctrl[15].val[6] = 0;
1380 state->CH_Ctrl[15].addr[7] = 16;
1381 state->CH_Ctrl[15].bit[7] = 5;
1382 state->CH_Ctrl[15].val[7] = 0;
1383 state->CH_Ctrl[15].addr[8] = 16;
1384 state->CH_Ctrl[15].bit[8] = 6;
1385 state->CH_Ctrl[15].val[8] = 0;
1386 state->CH_Ctrl[15].addr[9] = 16;
1387 state->CH_Ctrl[15].bit[9] = 7;
1388 state->CH_Ctrl[15].val[9] = 0;
1389 state->CH_Ctrl[15].addr[10] = 15;
1390 state->CH_Ctrl[15].bit[10] = 0;
1391 state->CH_Ctrl[15].val[10] = 0;
1392 state->CH_Ctrl[15].addr[11] = 15;
1393 state->CH_Ctrl[15].bit[11] = 1;
1394 state->CH_Ctrl[15].val[11] = 0;
1395 state->CH_Ctrl[15].addr[12] = 15;
1396 state->CH_Ctrl[15].bit[12] = 2;
1397 state->CH_Ctrl[15].val[12] = 0;
1398 state->CH_Ctrl[15].addr[13] = 15;
1399 state->CH_Ctrl[15].bit[13] = 3;
1400 state->CH_Ctrl[15].val[13] = 0;
1401 state->CH_Ctrl[15].addr[14] = 15;
1402 state->CH_Ctrl[15].bit[14] = 4;
1403 state->CH_Ctrl[15].val[14] = 0;
1404 state->CH_Ctrl[15].addr[15] = 15;
1405 state->CH_Ctrl[15].bit[15] = 5;
1406 state->CH_Ctrl[15].val[15] = 0;
1407 state->CH_Ctrl[15].addr[16] = 15;
1408 state->CH_Ctrl[15].bit[16] = 6;
1409 state->CH_Ctrl[15].val[16] = 1;
1410 state->CH_Ctrl[15].addr[17] = 15;
1411 state->CH_Ctrl[15].bit[17] = 7;
1412 state->CH_Ctrl[15].val[17] = 1;
1414 state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ;
1415 state->CH_Ctrl[16].size = 5 ;
1416 state->CH_Ctrl[16].addr[0] = 112;
1417 state->CH_Ctrl[16].bit[0] = 0;
1418 state->CH_Ctrl[16].val[0] = 0;
1419 state->CH_Ctrl[16].addr[1] = 112;
1420 state->CH_Ctrl[16].bit[1] = 1;
1421 state->CH_Ctrl[16].val[1] = 0;
1422 state->CH_Ctrl[16].addr[2] = 112;
1423 state->CH_Ctrl[16].bit[2] = 2;
1424 state->CH_Ctrl[16].val[2] = 0;
1425 state->CH_Ctrl[16].addr[3] = 112;
1426 state->CH_Ctrl[16].bit[3] = 3;
1427 state->CH_Ctrl[16].val[3] = 0;
1428 state->CH_Ctrl[16].addr[4] = 112;
1429 state->CH_Ctrl[16].bit[4] = 4;
1430 state->CH_Ctrl[16].val[4] = 1;
1432 state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ;
1433 state->CH_Ctrl[17].size = 1 ;
1434 state->CH_Ctrl[17].addr[0] = 14;
1435 state->CH_Ctrl[17].bit[0] = 7;
1436 state->CH_Ctrl[17].val[0] = 0;
1438 state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ;
1439 state->CH_Ctrl[18].size = 4 ;
1440 state->CH_Ctrl[18].addr[0] = 107;
1441 state->CH_Ctrl[18].bit[0] = 3;
1442 state->CH_Ctrl[18].val[0] = 0;
1443 state->CH_Ctrl[18].addr[1] = 107;
1444 state->CH_Ctrl[18].bit[1] = 4;
1445 state->CH_Ctrl[18].val[1] = 0;
1446 state->CH_Ctrl[18].addr[2] = 107;
1447 state->CH_Ctrl[18].bit[2] = 5;
1448 state->CH_Ctrl[18].val[2] = 0;
1449 state->CH_Ctrl[18].addr[3] = 107;
1450 state->CH_Ctrl[18].bit[3] = 6;
1451 state->CH_Ctrl[18].val[3] = 0;
1453 state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ;
1454 state->CH_Ctrl[19].size = 3 ;
1455 state->CH_Ctrl[19].addr[0] = 107;
1456 state->CH_Ctrl[19].bit[0] = 7;
1457 state->CH_Ctrl[19].val[0] = 1;
1458 state->CH_Ctrl[19].addr[1] = 106;
1459 state->CH_Ctrl[19].bit[1] = 0;
1460 state->CH_Ctrl[19].val[1] = 1;
1461 state->CH_Ctrl[19].addr[2] = 106;
1462 state->CH_Ctrl[19].bit[2] = 1;
1463 state->CH_Ctrl[19].val[2] = 1;
1465 state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ;
1466 state->CH_Ctrl[20].size = 11 ;
1467 state->CH_Ctrl[20].addr[0] = 109;
1468 state->CH_Ctrl[20].bit[0] = 2;
1469 state->CH_Ctrl[20].val[0] = 0;
1470 state->CH_Ctrl[20].addr[1] = 109;
1471 state->CH_Ctrl[20].bit[1] = 3;
1472 state->CH_Ctrl[20].val[1] = 0;
1473 state->CH_Ctrl[20].addr[2] = 109;
1474 state->CH_Ctrl[20].bit[2] = 4;
1475 state->CH_Ctrl[20].val[2] = 0;
1476 state->CH_Ctrl[20].addr[3] = 109;
1477 state->CH_Ctrl[20].bit[3] = 5;
1478 state->CH_Ctrl[20].val[3] = 0;
1479 state->CH_Ctrl[20].addr[4] = 109;
1480 state->CH_Ctrl[20].bit[4] = 6;
1481 state->CH_Ctrl[20].val[4] = 0;
1482 state->CH_Ctrl[20].addr[5] = 109;
1483 state->CH_Ctrl[20].bit[5] = 7;
1484 state->CH_Ctrl[20].val[5] = 0;
1485 state->CH_Ctrl[20].addr[6] = 108;
1486 state->CH_Ctrl[20].bit[6] = 0;
1487 state->CH_Ctrl[20].val[6] = 0;
1488 state->CH_Ctrl[20].addr[7] = 108;
1489 state->CH_Ctrl[20].bit[7] = 1;
1490 state->CH_Ctrl[20].val[7] = 0;
1491 state->CH_Ctrl[20].addr[8] = 108;
1492 state->CH_Ctrl[20].bit[8] = 2;
1493 state->CH_Ctrl[20].val[8] = 1;
1494 state->CH_Ctrl[20].addr[9] = 108;
1495 state->CH_Ctrl[20].bit[9] = 3;
1496 state->CH_Ctrl[20].val[9] = 1;
1497 state->CH_Ctrl[20].addr[10] = 108;
1498 state->CH_Ctrl[20].bit[10] = 4;
1499 state->CH_Ctrl[20].val[10] = 1;
1501 state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ;
1502 state->CH_Ctrl[21].size = 6 ;
1503 state->CH_Ctrl[21].addr[0] = 106;
1504 state->CH_Ctrl[21].bit[0] = 2;
1505 state->CH_Ctrl[21].val[0] = 0;
1506 state->CH_Ctrl[21].addr[1] = 106;
1507 state->CH_Ctrl[21].bit[1] = 3;
1508 state->CH_Ctrl[21].val[1] = 0;
1509 state->CH_Ctrl[21].addr[2] = 106;
1510 state->CH_Ctrl[21].bit[2] = 4;
1511 state->CH_Ctrl[21].val[2] = 0;
1512 state->CH_Ctrl[21].addr[3] = 106;
1513 state->CH_Ctrl[21].bit[3] = 5;
1514 state->CH_Ctrl[21].val[3] = 0;
1515 state->CH_Ctrl[21].addr[4] = 106;
1516 state->CH_Ctrl[21].bit[4] = 6;
1517 state->CH_Ctrl[21].val[4] = 0;
1518 state->CH_Ctrl[21].addr[5] = 106;
1519 state->CH_Ctrl[21].bit[5] = 7;
1520 state->CH_Ctrl[21].val[5] = 1;
1522 state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ;
1523 state->CH_Ctrl[22].size = 1 ;
1524 state->CH_Ctrl[22].addr[0] = 138;
1525 state->CH_Ctrl[22].bit[0] = 4;
1526 state->CH_Ctrl[22].val[0] = 1;
1528 state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ;
1529 state->CH_Ctrl[23].size = 1 ;
1530 state->CH_Ctrl[23].addr[0] = 17;
1531 state->CH_Ctrl[23].bit[0] = 5;
1532 state->CH_Ctrl[23].val[0] = 0;
1534 state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ;
1535 state->CH_Ctrl[24].size = 1 ;
1536 state->CH_Ctrl[24].addr[0] = 111;
1537 state->CH_Ctrl[24].bit[0] = 3;
1538 state->CH_Ctrl[24].val[0] = 0;
1540 state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ;
1541 state->CH_Ctrl[25].size = 1 ;
1542 state->CH_Ctrl[25].addr[0] = 112;
1543 state->CH_Ctrl[25].bit[0] = 7;
1544 state->CH_Ctrl[25].val[0] = 0;
1546 state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ;
1547 state->CH_Ctrl[26].size = 1 ;
1548 state->CH_Ctrl[26].addr[0] = 136;
1549 state->CH_Ctrl[26].bit[0] = 7;
1550 state->CH_Ctrl[26].val[0] = 0;
1552 state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ;
1553 state->CH_Ctrl[27].size = 1 ;
1554 state->CH_Ctrl[27].addr[0] = 149;
1555 state->CH_Ctrl[27].bit[0] = 7;
1556 state->CH_Ctrl[27].val[0] = 0;
1558 state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ;
1559 state->CH_Ctrl[28].size = 1 ;
1560 state->CH_Ctrl[28].addr[0] = 149;
1561 state->CH_Ctrl[28].bit[0] = 6;
1562 state->CH_Ctrl[28].val[0] = 0;
1564 state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ;
1565 state->CH_Ctrl[29].size = 1 ;
1566 state->CH_Ctrl[29].addr[0] = 149;
1567 state->CH_Ctrl[29].bit[0] = 5;
1568 state->CH_Ctrl[29].val[0] = 1;
1570 state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ;
1571 state->CH_Ctrl[30].size = 1 ;
1572 state->CH_Ctrl[30].addr[0] = 149;
1573 state->CH_Ctrl[30].bit[0] = 4;
1574 state->CH_Ctrl[30].val[0] = 1;
1576 state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ;
1577 state->CH_Ctrl[31].size = 1 ;
1578 state->CH_Ctrl[31].addr[0] = 149;
1579 state->CH_Ctrl[31].bit[0] = 3;
1580 state->CH_Ctrl[31].val[0] = 0;
1582 state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ;
1583 state->CH_Ctrl[32].size = 1 ;
1584 state->CH_Ctrl[32].addr[0] = 93;
1585 state->CH_Ctrl[32].bit[0] = 1;
1586 state->CH_Ctrl[32].val[0] = 0;
1588 state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ;
1589 state->CH_Ctrl[33].size = 1 ;
1590 state->CH_Ctrl[33].addr[0] = 93;
1591 state->CH_Ctrl[33].bit[0] = 0;
1592 state->CH_Ctrl[33].val[0] = 0;
1594 state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ;
1595 state->CH_Ctrl[34].size = 6 ;
1596 state->CH_Ctrl[34].addr[0] = 92;
1597 state->CH_Ctrl[34].bit[0] = 2;
1598 state->CH_Ctrl[34].val[0] = 0;
1599 state->CH_Ctrl[34].addr[1] = 92;
1600 state->CH_Ctrl[34].bit[1] = 3;
1601 state->CH_Ctrl[34].val[1] = 0;
1602 state->CH_Ctrl[34].addr[2] = 92;
1603 state->CH_Ctrl[34].bit[2] = 4;
1604 state->CH_Ctrl[34].val[2] = 0;
1605 state->CH_Ctrl[34].addr[3] = 92;
1606 state->CH_Ctrl[34].bit[3] = 5;
1607 state->CH_Ctrl[34].val[3] = 0;
1608 state->CH_Ctrl[34].addr[4] = 92;
1609 state->CH_Ctrl[34].bit[4] = 6;
1610 state->CH_Ctrl[34].val[4] = 0;
1611 state->CH_Ctrl[34].addr[5] = 92;
1612 state->CH_Ctrl[34].bit[5] = 7;
1613 state->CH_Ctrl[34].val[5] = 0;
1615 state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ;
1616 state->CH_Ctrl[35].size = 6 ;
1617 state->CH_Ctrl[35].addr[0] = 93;
1618 state->CH_Ctrl[35].bit[0] = 2;
1619 state->CH_Ctrl[35].val[0] = 0;
1620 state->CH_Ctrl[35].addr[1] = 93;
1621 state->CH_Ctrl[35].bit[1] = 3;
1622 state->CH_Ctrl[35].val[1] = 0;
1623 state->CH_Ctrl[35].addr[2] = 93;
1624 state->CH_Ctrl[35].bit[2] = 4;
1625 state->CH_Ctrl[35].val[2] = 0;
1626 state->CH_Ctrl[35].addr[3] = 93;
1627 state->CH_Ctrl[35].bit[3] = 5;
1628 state->CH_Ctrl[35].val[3] = 0;
1629 state->CH_Ctrl[35].addr[4] = 93;
1630 state->CH_Ctrl[35].bit[4] = 6;
1631 state->CH_Ctrl[35].val[4] = 0;
1632 state->CH_Ctrl[35].addr[5] = 93;
1633 state->CH_Ctrl[35].bit[5] = 7;
1634 state->CH_Ctrl[35].val[5] = 0;
1637 state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ;
1638 state->CH_Ctrl[36].size = 1 ;
1639 state->CH_Ctrl[36].addr[0] = 109;
1640 state->CH_Ctrl[36].bit[0] = 1;
1641 state->CH_Ctrl[36].val[0] = 1;
1643 state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ;
1644 state->CH_Ctrl[37].size = 2 ;
1645 state->CH_Ctrl[37].addr[0] = 112;
1646 state->CH_Ctrl[37].bit[0] = 5;
1647 state->CH_Ctrl[37].val[0] = 0;
1648 state->CH_Ctrl[37].addr[1] = 112;
1649 state->CH_Ctrl[37].bit[1] = 6;
1650 state->CH_Ctrl[37].val[1] = 0;
1652 state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ;
1653 state->CH_Ctrl[38].size = 1 ;
1654 state->CH_Ctrl[38].addr[0] = 65;
1655 state->CH_Ctrl[38].bit[0] = 1;
1656 state->CH_Ctrl[38].val[0] = 0;
1694 struct mxl5005s_state *state = fe->tuner_priv;
1696 state->Mode = Mode;
1697 state->IF_Mode = IF_mode;
1698 state->Chan_Bandwidth = Bandwidth;
1699 state->IF_OUT = IF_out;
1700 state->Fxtal = Fxtal;
1701 state->AGC_Mode = AGC_Mode;
1702 state->TOP = TOP;
1703 state->IF_OUT_LOAD = IF_OUT_LOAD;
1704 state->CLOCK_OUT = CLOCK_OUT;
1705 state->DIV_OUT = DIV_OUT;
1706 state->CAPSELECT = CAPSELECT;
1707 state->EN_RSSI = EN_RSSI;
1708 state->Mod_Type = Mod_Type;
1709 state->TF_Type = TF_Type;
1722 struct mxl5005s_state *state = fe->tuner_priv;
1723 if (state->Mode == 1) /* Digital Mode */
1724 state->IF_LO = state->IF_OUT;
1726 if (state->IF_Mode == 0) /* Analog Zero IF mode */
1727 state->IF_LO = state->IF_OUT + 400000;
1729 state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2;
1735 struct mxl5005s_state *state = fe->tuner_priv;
1737 if (state->Mode == 1) /* Digital Mode */ {
1739 state->RF_LO = state->RF_IN;
1741 state->TG_LO = state->RF_IN - 750000;
1743 if (state->IF_Mode == 0) /* Analog Zero IF mode */ {
1744 state->RF_LO = state->RF_IN - 400000;
1745 state->TG_LO = state->RF_IN - 1750000;
1747 state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2;
1748 state->TG_LO = state->RF_IN -
1749 state->Chan_Bandwidth + 500000;
1768 struct mxl5005s_state *state = fe->tuner_priv;
1774 status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0);
1777 status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1);
1778 status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2);
1779 status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0);
1780 status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1);
1784 if (state->Mode) { /* Digital Mode */
1785 switch (state->Chan_Bandwidth) {
1798 switch (state->Chan_Bandwidth) {
1801 (state->IF_Mode ? 0 : 3));
1805 (state->IF_Mode ? 1 : 4));
1809 (state->IF_Mode ? 2 : 5));
1815 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8);
1817 RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1);
1818 status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0);
1821 if (state->AGC_Mode == 0) /* Dual AGC */ {
1825 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
1827 if (state->TOP == 55) /* TOP == 5.5 */
1830 if (state->TOP == 72) /* TOP == 7.2 */
1833 if (state->TOP == 92) /* TOP == 9.2 */
1836 if (state->TOP == 110) /* TOP == 11.0 */
1839 if (state->TOP == 129) /* TOP == 12.9 */
1842 if (state->TOP == 147) /* TOP == 14.7 */
1845 if (state->TOP == 168) /* TOP == 16.8 */
1848 if (state->TOP == 194) /* TOP == 19.4 */
1851 if (state->TOP == 212) /* TOP == 21.2 */
1854 if (state->TOP == 232) /* TOP == 23.2 */
1857 if (state->TOP == 252) /* TOP == 25.2 */
1860 if (state->TOP == 271) /* TOP == 27.1 */
1863 if (state->TOP == 292) /* TOP == 29.2 */
1866 if (state->TOP == 317) /* TOP == 31.7 */
1869 if (state->TOP == 349) /* TOP == 34.9 */
1876 if (state->IF_OUT_LOAD == 200) {
1880 if (state->IF_OUT_LOAD == 300) {
1888 if (state->Mode) { /* Digital Mode */
1889 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) {
1895 if ((state->IF_OUT == 36125000UL) ||
1896 (state->IF_OUT == 36150000UL)) {
1902 if (state->IF_OUT > 36150000UL) {
1909 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) {
1915 if (state->IF_OUT > 5000000UL) {
1924 if (state->CLOCK_OUT)
1929 if (state->DIV_OUT == 1)
1931 if (state->DIV_OUT == 0)
1935 if (state->CAPSELECT)
1940 if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
1942 if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
1945 if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
1947 if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL)
1951 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */
1960 MXL_Ceiling(state->Fxtal, 1000000));
1965 if (state->EN_RSSI) {
1984 if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ {
1985 state->AGC_Mode = 1; /* Single AGC Mode */
2001 if (state->IF_OUT <= 6280000UL) /* Low IF */
2007 if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ {
2008 state->AGC_Mode = 1; /* Single AGC Mode */
2028 if (state->IF_OUT <= 6280000UL) /* Low IF */
2033 if (state->Mod_Type == MXL_QAM) /* QAM Mode */ {
2034 state->Mode = MXL_DIGITAL_MODE;
2036 /* state->AGC_Mode = 1; */ /* Single AGC Mode */
2051 if (state->IF_OUT <= 6280000UL) /* Low IF */
2058 if (state->Mod_Type == MXL_ANALOG_CABLE) {
2060 /* state->Mode = MXL_DIGITAL_MODE; */
2062 state->AGC_Mode = 1; /* Single AGC Mode */
2075 if (state->Mod_Type == MXL_ANALOG_OTA) {
2077 /* state->Mode = MXL_ANALOG_MODE; */
2094 if (state->EN_RSSI == 0) {
2106 struct mxl5005s_state *state = fe->tuner_priv;
2113 if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
2115 if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
2119 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ {
2120 if (state->IF_LO == 41000000UL) {
2125 if (state->IF_LO == 47000000UL) {
2130 if (state->IF_LO == 54000000UL) {
2135 if (state->IF_LO == 60000000UL) {
2140 if (state->IF_LO == 39250000UL) {
2145 if (state->IF_LO == 39650000UL) {
2150 if (state->IF_LO == 40150000UL) {
2155 if (state->IF_LO == 40650000UL) {
2162 if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) {
2163 if (state->IF_LO == 57000000UL) {
2168 if (state->IF_LO == 44000000UL) {
2173 if (state->IF_LO == 43750000UL) {
2178 if (state->IF_LO == 36650000UL) {
2183 if (state->IF_LO == 36150000UL) {
2188 if (state->IF_LO == 36000000UL) {
2193 if (state->IF_LO == 35250000UL) {
2198 if (state->IF_LO == 34750000UL) {
2203 if (state->IF_LO == 6280000UL) {
2208 if (state->IF_LO == 5000000UL) {
2213 if (state->IF_LO == 4500000UL) {
2218 if (state->IF_LO == 4570000UL) {
2223 if (state->IF_LO == 4000000UL) {
2228 if (state->IF_LO == 57400000UL) {
2233 if (state->IF_LO == 44400000UL) {
2238 if (state->IF_LO == 44150000UL) {
2243 if (state->IF_LO == 37050000UL) {
2248 if (state->IF_LO == 36550000UL) {
2253 if (state->IF_LO == 36125000UL) {
2258 if (state->IF_LO == 6000000UL) {
2263 if (state->IF_LO == 5400000UL) {
2268 if (state->IF_LO == 5380000UL) {
2273 if (state->IF_LO == 5200000UL) {
2278 if (state->IF_LO == 4900000UL) {
2283 if (state->IF_LO == 4400000UL) {
2288 if (state->IF_LO == 4063000UL) /* add for 2.6.8 */ {
2296 intModVal = Fref / (state->Fxtal * Kdbl/2);
2299 fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) *
2302 fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000);
2310 struct mxl5005s_state *state = fe->tuner_priv;
2321 state->RF_IN = RF_Freq;
2325 if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
2327 if (state->Fxtal > 22000000 && state->Fxtal <= 32000000)
2339 if (state->RF_LO < 40000000UL)
2342 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2349 if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2356 if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2363 if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2370 if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2377 if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) {
2384 if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) {
2391 if (state->RF_LO > 900000000UL)
2396 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2400 if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2404 if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2408 if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2412 if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2416 if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) {
2420 if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) {
2424 if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) {
2428 if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) {
2432 if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) {
2436 if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) {
2440 if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) {
2444 if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) {
2448 if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) {
2452 if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) {
2456 if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) {
2476 if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) {
2489 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2502 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2515 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2528 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2541 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2554 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2567 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2580 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2593 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2606 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2624 E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ;
2628 E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000);
2632 E5 = ((2<<17)*(state->RF_LO/10000*divider_val -
2633 (E4*(2*state->Fxtal*Kdbl_RF)/10000))) /
2634 (2*state->Fxtal*Kdbl_RF/10000);
2639 E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ;
2659 if (state->TG_LO < 33000000UL)
2664 if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) {
2673 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2682 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2691 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2700 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2709 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2718 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2727 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2736 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2743 tg_divval = (state->TG_LO*divider_val/100000) *
2744 (MXL_Ceiling(state->Fxtal, 1000000) * 100) /
2745 (state->Fxtal/1000);
2749 if (state->TG_LO > 600000000UL)
2759 Fref_TG = (state->Fxtal/1000) / MXL_Ceiling(state->Fxtal, 1000000);
2762 Fvco = (state->TG_LO/10000) * divider_val * Fref_TG;
2776 * u32 Xtal_Int = MXL_GetXtalInt(state->Fxtal);
2778 * ((state->TG_LO/10000)*divider_val *
2779 * (state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 *
2786 if (state->Mod_Type == MXL_QAM) {
2787 if (state->config->qam_gain != 0)
2789 state->config->qam_gain);
2790 else if (state->RF_IN < 680000000)
2797 if (state->TF_Type == MXL_TF_OFF) {
2806 if (state->TF_Type == MXL_TF_C) /* Tracking Filter type C */ {
2810 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
2817 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
2824 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
2831 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
2838 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
2845 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
2852 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
2859 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
2866 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
2875 if (state->TF_Type == MXL_TF_C_H) {
2880 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
2886 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
2892 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
2898 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
2904 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
2910 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
2916 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
2922 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
2928 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
2936 if (state->TF_Type == MXL_TF_D) { /* Tracking Filter type D */
2940 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
2946 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
2952 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
2958 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
2964 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
2970 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
2976 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
2984 if (state->TF_Type == MXL_TF_D_L) {
2990 if (state->RF_IN >= 471000000 &&
2991 (state->RF_IN - 471000000)%6000000 != 0) {
3000 if (state->RF_IN >= 43000000 &&
3001 state->RF_IN < 140000000) {
3008 if (state->RF_IN >= 140000000 &&
3009 state->RF_IN < 240000000) {
3015 if (state->RF_IN >= 240000000 &&
3016 state->RF_IN < 340000000) {
3022 if (state->RF_IN >= 340000000 &&
3023 state->RF_IN < 430000000) {
3029 if (state->RF_IN >= 430000000 &&
3030 state->RF_IN < 470000000) {
3036 if (state->RF_IN >= 470000000 &&
3037 state->RF_IN < 570000000) {
3043 if (state->RF_IN >= 570000000 &&
3044 state->RF_IN < 620000000) {
3050 if (state->RF_IN >= 620000000 &&
3051 state->RF_IN < 760000000) {
3057 if (state->RF_IN >= 760000000 &&
3058 state->RF_IN <= 900000000) {
3067 if (state->TF_Type == MXL_TF_E) /* Tracking Filter type E */ {
3071 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3077 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3083 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
3089 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
3095 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
3101 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
3107 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
3115 if (state->TF_Type == MXL_TF_F) {
3120 if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) {
3126 if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) {
3132 if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) {
3138 if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) {
3144 if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) {
3150 if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) {
3156 if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) {
3164 if (state->TF_Type == MXL_TF_E_2) {
3169 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3175 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3181 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
3187 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3193 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
3199 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
3205 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
3213 if (state->TF_Type == MXL_TF_G) {
3218 if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) {
3225 if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) {
3231 if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) {
3237 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3243 if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) {
3249 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
3255 if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) {
3261 if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) {
3269 if (state->TF_Type == MXL_TF_E_NA) {
3275 if (state->RF_IN >= 471000000 &&
3276 (state->RF_IN - 471000000)%6000000 != 0) {
3308 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3315 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3321 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
3327 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3333 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
3339 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
3345 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
3374 if (GPIO_Val == 3) { /* tri-state */
3388 if (GPIO_Val == 3) { /* tri-state */
3416 struct mxl5005s_state *state = fe->tuner_priv;
3422 for (i = 0; i < state->Init_Ctrl_Num; i++) {
3424 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3426 u16 size = min_t(u16, state->Init_Ctrl[i].size,
3427 ARRAY_SIZE(state->Init_Ctrl[i].val));
3431 state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3432 MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]),
3433 (u8)(state->Init_Ctrl[i].bit[j]),
3443 for (i = 0; i < state->CH_Ctrl_Num; i++) {
3445 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
3447 u16 size = min_t(u16, state->CH_Ctrl[i].size,
3448 ARRAY_SIZE(state->CH_Ctrl[i].val));
3452 state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3453 MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]),
3454 (u8)(state->CH_Ctrl[i].bit[j]),
3465 for (i = 0; i < state->MXL_Ctrl_Num; i++) {
3467 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
3469 highLimit = (1 << state->MXL_Ctrl[i].size);
3471 for (j = 0; j < state->MXL_Ctrl[i].size; j++) {
3472 state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3473 MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]),
3474 (u8)(state->MXL_Ctrl[i].bit[j]),
3488 struct mxl5005s_state *state = fe->tuner_priv;
3492 if (RegNum == state->TunerRegs[i].Reg_Num) {
3493 *RegVal = (u8)(state->TunerRegs[i].Reg_Val);
3503 struct mxl5005s_state *state = fe->tuner_priv;
3507 for (i = 0; i < state->Init_Ctrl_Num ; i++) {
3509 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3512 for (k = 0; k < state->Init_Ctrl[i].size; k++)
3513 ctrlVal += state->Init_Ctrl[i].val[k] * (1<<k);
3519 for (i = 0; i < state->CH_Ctrl_Num ; i++) {
3521 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
3524 for (k = 0; k < state->CH_Ctrl[i].size; k++)
3525 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
3533 for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
3535 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
3538 for (k = 0; k < state->MXL_Ctrl[i].size; k++)
3539 ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k);
3552 struct mxl5005s_state *state = fe->tuner_priv;
3563 for (i = 0; i < state->TunerRegs_Num; i++) {
3564 if (state->TunerRegs[i].Reg_Num == address) {
3566 state->TunerRegs[i].Reg_Val |= OR_MAP[bit];
3568 state->TunerRegs[i].Reg_Val &= AND_MAP[bit];
3656 static u16 MXL_GetMasterControl(u8 *MasterReg, int state)
3658 if (state == 1) /* Load_Start */
3660 if (state == 2) /* Power_Down */
3662 if (state == 3) /* Synth_Reset */
3664 if (state == 4) /* Seq_Off */
3673 struct mxl5005s_state *state = fe->tuner_priv;
3684 if (state->Mode == 0 && state->IF_Mode == 1) {
3692 if (state->Mode == 0 && state->IF_Mode == 0) {
3700 if (state->Mode == 1) /* Digital Mode */ {
3720 if (state->Mode == 0 && state->IF_Mode == 1) {
3728 if (state->Mode == 0 && state->IF_Mode == 0) {
3736 if (state->Mode == 1) /* Digital Mode */ {
3756 if (state->Mode == 0 && state->IF_Mode == 1) {
3764 if (state->Mode == 0 && state->IF_Mode == 0) {
3772 if (state->Mode == 1) /* Digital Mode */ {
3792 if (state->Mode == 0 && state->IF_Mode == 1) {
3800 if (state->Mode == 0 && state->IF_Mode == 0) {
3808 if (state->Mode == 1) /* Digital Mode */ {
3822 struct mxl5005s_state *state = fe->tuner_priv;
3841 struct mxl5005s_state *state = fe->tuner_priv;
3845 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
3853 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
3869 struct mxl5005s_state *state = fe->tuner_priv;
3871 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
3879 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
3910 struct mxl5005s_state *state = fe->tuner_priv;
3913 state->current_mode = MXL_QAM;
3920 struct mxl5005s_state *state = fe->tuner_priv;
3944 ByteTable[0] |= state->config->AgcMasterByte;
3964 struct mxl5005s_state *state = fe->tuner_priv;
3965 struct mxl5005s_config *c = state->config;
3992 struct mxl5005s_state *state = fe->tuner_priv;
4029 if (req_mode != state->current_mode ||
4030 req_bw != state->Chan_Bandwidth) {
4031 state->current_mode = req_mode;
4047 struct mxl5005s_state *state = fe->tuner_priv;
4050 *frequency = state->RF_IN;
4057 struct mxl5005s_state *state = fe->tuner_priv;
4060 *bandwidth = state->Chan_Bandwidth;
4067 struct mxl5005s_state *state = fe->tuner_priv;
4070 *frequency = state->IF_OUT;
4103 struct mxl5005s_state *state = NULL;
4106 state = kzalloc(sizeof(struct mxl5005s_state), GFP_KERNEL);
4107 if (state == NULL)
4110 state->frontend = fe;
4111 state->config = config;
4112 state->i2c = i2c;
4120 fe->tuner_priv = state;