Lines Matching refs:ir
8 * Based on sun5i-ir.c:
21 #define SUNXI_IR_DEV "sunxi-ir"
62 #define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
105 struct sunxi_ir *ir = dev_id;
108 status = readl(ir->base + SUNXI_IR_RXSTA_REG);
111 writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
117 rc = rc > ir->fifo_size ? ir->fifo_size : rc;
121 dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
124 ir->rc->rx_resolution;
125 ir_raw_event_store_with_filter(ir->rc, &rawir);
130 ir_raw_event_overflow(ir->rc);
132 ir_raw_event_set_idle(ir->rc, true);
133 ir_raw_event_handle(ir->rc);
135 ir_raw_event_handle(ir->rc);
157 struct sunxi_ir *ir = rc_dev->priv;
158 unsigned int base_clk = clk_get_rate(ir->clk);
166 ir->base + SUNXI_IR_CIR_REG);
175 struct sunxi_ir *ir = dev_get_drvdata(dev);
179 ret = reset_control_deassert(ir->rst);
183 ret = clk_prepare_enable(ir->apb_clk);
189 ret = clk_prepare_enable(ir->clk);
191 dev_err(dev, "failed to enable ir clk\n");
196 writel(REG_CTL_MD, ir->base + SUNXI_IR_CTL_REG);
199 sunxi_ir_set_timeout(ir->rc, ir->rc->timeout);
202 writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG);
205 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
212 REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1),
213 ir->base + SUNXI_IR_RXINT_REG);
216 tmp = readl(ir->base + SUNXI_IR_CTL_REG);
217 writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG);
222 clk_disable_unprepare(ir->apb_clk);
224 reset_control_assert(ir->rst);
231 struct sunxi_ir *ir = dev_get_drvdata(dev);
233 clk_disable_unprepare(ir->clk);
234 clk_disable_unprepare(ir->apb_clk);
235 reset_control_assert(ir->rst);
259 struct sunxi_ir *ir;
262 ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
263 if (!ir)
272 ir->fifo_size = quirks->fifo_size;
275 ir->apb_clk = devm_clk_get(dev, "apb");
276 if (IS_ERR(ir->apb_clk)) {
278 return PTR_ERR(ir->apb_clk);
280 ir->clk = devm_clk_get(dev, "ir");
281 if (IS_ERR(ir->clk)) {
282 dev_err(dev, "failed to get a ir clock.\n");
283 return PTR_ERR(ir->clk);
291 ir->rst = devm_reset_control_get_exclusive(dev, NULL);
292 if (IS_ERR(ir->rst))
293 return PTR_ERR(ir->rst);
296 ret = clk_set_rate(ir->clk, b_clk_freq);
298 dev_err(dev, "set ir base clock failed!\n");
304 ir->base = devm_platform_ioremap_resource(pdev, 0);
305 if (IS_ERR(ir->base)) {
306 return PTR_ERR(ir->base);
309 ir->rc = rc_allocate_device(RC_DRIVER_IR_RAW);
310 if (!ir->rc) {
315 ir->rc->priv = ir;
316 ir->rc->device_name = SUNXI_IR_DEV;
317 ir->rc->input_phys = "sunxi-ir/input0";
318 ir->rc->input_id.bustype = BUS_HOST;
319 ir->rc->input_id.vendor = 0x0001;
320 ir->rc->input_id.product = 0x0001;
321 ir->rc->input_id.version = 0x0100;
322 ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL);
323 ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
324 ir->rc->dev.parent = dev;
325 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
327 ir->rc->rx_resolution = (USEC_PER_SEC / (b_clk_freq / 64));
328 ir->rc->timeout = IR_DEFAULT_TIMEOUT;
329 ir->rc->min_timeout = sunxi_ithr_to_usec(b_clk_freq, 0);
330 ir->rc->max_timeout = sunxi_ithr_to_usec(b_clk_freq, 255);
331 ir->rc->s_timeout = sunxi_ir_set_timeout;
332 ir->rc->driver_name = SUNXI_IR_DEV;
334 ret = rc_register_device(ir->rc);
340 platform_set_drvdata(pdev, ir);
343 ir->irq = platform_get_irq(pdev, 0);
344 if (ir->irq < 0) {
345 ret = ir->irq;
349 ret = devm_request_irq(dev, ir->irq, sunxi_ir_irq, 0, SUNXI_IR_DEV, ir);
363 rc_free_device(ir->rc);
370 struct sunxi_ir *ir = platform_get_drvdata(pdev);
372 rc_unregister_device(ir->rc);
398 .compatible = "allwinner,sun4i-a10-ir",
402 .compatible = "allwinner,sun5i-a13-ir",
406 .compatible = "allwinner,sun6i-a31-ir",