Lines Matching defs:nvt
37 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt);
46 static inline struct device *nvt_get_dev(const struct nvt_dev *nvt)
48 return nvt->rdev->dev.parent;
51 static inline bool is_w83667hg(struct nvt_dev *nvt)
53 return nvt->chip_ver == NVT_W83667HG;
57 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
59 outb(reg, nvt->cr_efir);
60 outb(val, nvt->cr_efdr);
64 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
66 outb(reg, nvt->cr_efir);
67 return inb(nvt->cr_efdr);
71 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
73 u8 tmp = nvt_cr_read(nvt, reg) | val;
74 nvt_cr_write(nvt, tmp, reg);
78 static inline int nvt_efm_enable(struct nvt_dev *nvt)
80 if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME))
84 outb(EFER_EFM_ENABLE, nvt->cr_efir);
85 outb(EFER_EFM_ENABLE, nvt->cr_efir);
91 static inline void nvt_efm_disable(struct nvt_dev *nvt)
93 outb(EFER_EFM_DISABLE, nvt->cr_efir);
95 release_region(nvt->cr_efir, 2);
103 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
105 nvt_cr_write(nvt, ldev, CR_LOGICAL_DEV_SEL);
109 static inline void nvt_enable_logical_dev(struct nvt_dev *nvt, u8 ldev)
111 nvt_efm_enable(nvt);
112 nvt_select_logical_dev(nvt, ldev);
113 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
114 nvt_efm_disable(nvt);
118 static inline void nvt_disable_logical_dev(struct nvt_dev *nvt, u8 ldev)
120 nvt_efm_enable(nvt);
121 nvt_select_logical_dev(nvt, ldev);
122 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
123 nvt_efm_disable(nvt);
127 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
129 outb(val, nvt->cir_addr + offset);
133 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
135 return inb(nvt->cir_addr + offset);
139 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
142 outb(val, nvt->cir_wake_addr + offset);
146 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
148 return inb(nvt->cir_wake_addr + offset);
152 static void nvt_set_ioaddr(struct nvt_dev *nvt, unsigned long *ioaddr)
156 old_addr = nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8;
157 old_addr |= nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO);
162 nvt_cr_write(nvt, *ioaddr >> 8, CR_CIR_BASE_ADDR_HI);
163 nvt_cr_write(nvt, *ioaddr & 0xff, CR_CIR_BASE_ADDR_LO);
171 struct nvt_dev *nvt = dev->priv;
178 spin_lock_irqsave(&nvt->lock, flags);
180 nvt_clear_cir_wake_fifo(nvt);
181 nvt_cir_wake_reg_write(nvt, count, CIR_WAKE_FIFO_CMP_DEEP);
182 nvt_cir_wake_reg_write(nvt, tolerance, CIR_WAKE_FIFO_CMP_TOL);
184 config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
187 nvt_cir_wake_reg_write(nvt, config | CIR_WAKE_IRCON_MODE1,
196 nvt_cir_wake_reg_write(nvt, wbuf[i], CIR_WAKE_WR_FIFO_DATA);
198 nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
200 spin_unlock_irqrestore(&nvt->lock, flags);
208 struct nvt_dev *nvt = rc_dev->priv;
214 spin_lock_irqsave(&nvt->lock, flags);
216 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
220 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX))
221 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
224 duration = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
231 spin_unlock_irqrestore(&nvt->lock, flags);
280 static void cir_dump_regs(struct nvt_dev *nvt)
282 nvt_efm_enable(nvt);
283 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
287 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
289 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
290 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
292 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
294 nvt_efm_disable(nvt);
297 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
298 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
299 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
300 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
301 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
302 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
303 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
304 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
305 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
306 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
307 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
308 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
309 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
310 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
311 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
312 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
316 static void cir_wake_dump_regs(struct nvt_dev *nvt)
320 nvt_efm_enable(nvt);
321 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
326 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
328 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
329 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
331 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
333 nvt_efm_disable(nvt);
337 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
339 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
341 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
343 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
345 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
347 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
349 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
351 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
353 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
355 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
357 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
359 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
361 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
363 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
365 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
367 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
369 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
374 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
378 static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id)
384 nvt->chip_ver = nvt_chips[i].chip_ver;
393 static int nvt_hw_detect(struct nvt_dev *nvt)
395 struct device *dev = nvt_get_dev(nvt);
399 nvt_efm_enable(nvt);
402 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
403 if (nvt->chip_major == 0xff) {
404 nvt_efm_disable(nvt);
405 nvt->cr_efir = CR_EFIR2;
406 nvt->cr_efdr = CR_EFDR2;
407 nvt_efm_enable(nvt);
408 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
410 nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
412 nvt_efm_disable(nvt);
414 chip_id = nvt->chip_major << 8 | nvt->chip_minor;
420 chip_name = nvt_find_chip(nvt, chip_id);
426 nvt->chip_major, nvt->chip_minor);
429 chip_name, nvt->chip_major, nvt->chip_minor);
434 static void nvt_cir_ldev_init(struct nvt_dev *nvt)
438 if (is_w83667hg(nvt)) {
449 val = nvt_cr_read(nvt, psreg);
452 nvt_cr_write(nvt, val, psreg);
455 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
457 nvt_set_ioaddr(nvt, &nvt->cir_addr);
459 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
462 nvt->cir_addr, nvt->cir_irq);
465 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
468 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
469 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
472 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
475 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
478 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
480 nvt_set_ioaddr(nvt, &nvt->cir_wake_addr);
483 nvt->cir_wake_addr);
487 static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
489 u8 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
490 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
494 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
498 config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
501 nvt_cir_wake_reg_write(nvt, config & ~CIR_WAKE_IRCON_MODE0,
504 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
505 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
508 nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
512 static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
516 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
517 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
521 static void nvt_set_cir_iren(struct nvt_dev *nvt)
526 nvt_cir_reg_write(nvt, iren, CIR_IREN);
529 static void nvt_cir_regs_init(struct nvt_dev *nvt)
531 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
534 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
535 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
538 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
542 nvt_clear_cir_fifo(nvt);
543 nvt_clear_tx_fifo(nvt);
545 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
548 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
550 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
556 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 |
562 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
565 static void nvt_enable_wake(struct nvt_dev *nvt)
569 nvt_efm_enable(nvt);
571 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
572 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
573 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
575 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
576 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
578 nvt_efm_disable(nvt);
580 spin_lock_irqsave(&nvt->lock, flags);
582 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
586 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
587 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
589 spin_unlock_irqrestore(&nvt->lock, flags);
594 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
599 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
600 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
602 for (i = 0; i < nvt->pkts; i++) {
603 if (nvt->buf[i] & BUF_PULSE_BIT)
604 duration += nvt->buf[i] & BUF_LEN_MASK;
610 dev_notice(nvt_get_dev(nvt),
684 static void nvt_dump_rx_buf(struct nvt_dev *nvt)
688 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
689 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
690 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
706 static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
715 nvt_dump_rx_buf(nvt);
717 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
719 for (i = 0; i < nvt->pkts; i++) {
720 sample = nvt->buf[i];
728 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
731 nvt->pkts = 0;
734 ir_raw_event_handle(nvt->rdev);
739 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
741 dev_warn(nvt_get_dev(nvt), "RX FIFO overrun detected, flushing data!");
743 nvt->pkts = 0;
744 nvt_clear_cir_fifo(nvt);
745 ir_raw_event_overflow(nvt->rdev);
749 static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
755 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
761 nvt->buf[i] = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
763 nvt->pkts = fifocount;
764 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
766 nvt_process_rx_ir_data(nvt);
789 struct nvt_dev *nvt = data;
794 spin_lock(&nvt->lock);
809 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
810 iren = nvt_cir_reg_read(nvt, CIR_IREN);
816 spin_unlock(&nvt->lock);
825 spin_unlock(&nvt->lock);
831 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
832 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
837 nvt_handle_rx_fifo_overrun(nvt);
839 nvt_get_rx_ir_data(nvt);
841 spin_unlock(&nvt->lock);
847 static void nvt_enable_cir(struct nvt_dev *nvt)
852 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
854 spin_lock_irqsave(&nvt->lock, flags);
860 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
865 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
868 nvt_set_cir_iren(nvt);
870 spin_unlock_irqrestore(&nvt->lock, flags);
873 static void nvt_disable_cir(struct nvt_dev *nvt)
877 spin_lock_irqsave(&nvt->lock, flags);
880 nvt_cir_reg_write(nvt, 0, CIR_IREN);
883 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
886 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
889 nvt_clear_cir_fifo(nvt);
890 nvt_clear_tx_fifo(nvt);
892 spin_unlock_irqrestore(&nvt->lock, flags);
895 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
900 struct nvt_dev *nvt = dev->priv;
902 nvt_enable_cir(nvt);
909 struct nvt_dev *nvt = dev->priv;
911 nvt_disable_cir(nvt);
917 struct nvt_dev *nvt;
921 nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL);
922 if (!nvt)
926 nvt->rdev = devm_rc_allocate_device(&pdev->dev, RC_DRIVER_IR_RAW);
927 if (!nvt->rdev)
929 rdev = nvt->rdev;
956 nvt->cir_addr = pnp_port_start(pdev, 0);
957 nvt->cir_irq = pnp_irq(pdev, 0);
959 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
961 nvt->cr_efir = CR_EFIR;
962 nvt->cr_efdr = CR_EFDR;
964 spin_lock_init(&nvt->lock);
966 pnp_set_drvdata(pdev, nvt);
968 ret = nvt_hw_detect(nvt);
973 nvt_efm_enable(nvt);
974 nvt_cir_ldev_init(nvt);
975 nvt_cir_wake_ldev_init(nvt);
976 nvt_efm_disable(nvt);
982 nvt_cir_regs_init(nvt);
983 nvt_cir_wake_regs_init(nvt);
986 rdev->priv = nvt;
997 rdev->input_id.product = nvt->chip_major;
998 rdev->input_id.version = nvt->chip_minor;
1013 if (!devm_request_region(&pdev->dev, nvt->cir_addr,
1017 ret = devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr,
1018 IRQF_SHARED, NVT_DRIVER_NAME, nvt);
1022 if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr,
1034 cir_dump_regs(nvt);
1035 cir_wake_dump_regs(nvt);
1043 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1045 device_remove_file(&nvt->rdev->dev, &dev_attr_wakeup_data);
1047 nvt_disable_cir(nvt);
1050 nvt_enable_wake(nvt);
1055 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1059 mutex_lock(&nvt->rdev->lock);
1060 if (nvt->rdev->users)
1061 nvt_disable_cir(nvt);
1062 mutex_unlock(&nvt->rdev->lock);
1065 nvt_enable_wake(nvt);
1072 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1076 nvt_cir_regs_init(nvt);
1077 nvt_cir_wake_regs_init(nvt);
1079 mutex_lock(&nvt->rdev->lock);
1080 if (nvt->rdev->users)
1081 nvt_enable_cir(nvt);
1082 mutex_unlock(&nvt->rdev->lock);
1089 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1091 nvt_enable_wake(nvt);