Lines Matching refs:ir
147 static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i)
149 return ir->data->regs[MTK_CHKDATA_REG] + 4 * i;
152 static inline u32 mtk_chk_period(struct mtk_ir *ir)
160 val = DIV_ROUND_CLOSEST(clk_get_rate(ir->bus),
161 USEC_PER_SEC * ir->data->div / MTK_IR_SAMPLE);
163 dev_dbg(ir->dev, "@pwm clk = \t%lu\n",
164 clk_get_rate(ir->bus) / ir->data->div);
165 dev_dbg(ir->dev, "@chkperiod = %08x\n", val);
170 static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg)
174 tmp = __raw_readl(ir->base + reg);
176 __raw_writel(tmp, ir->base + reg);
179 static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg)
181 __raw_writel(val, ir->base + reg);
184 static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg)
186 return __raw_readl(ir->base + reg);
189 static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask)
193 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
194 mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]);
197 static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask)
201 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
202 mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]);
208 struct mtk_ir *ir = dev_id;
228 val = mtk_r32(ir, mtk_chkdata_reg(ir, i));
229 dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val);
236 ir_raw_event_store_with_filter(ir->rc, &rawir);
245 * ir-rc-raw to decode. That helps it is possible that it
252 ir_raw_event_store_with_filter(ir->rc, &rawir);
255 ir_raw_event_handle(ir->rc);
261 mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]);
264 mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR,
265 ir->data->regs[MTK_IRINT_CLR_REG]);
297 struct mtk_ir *ir;
302 ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL);
303 if (!ir)
306 ir->dev = dev;
307 ir->data = of_device_get_match_data(dev);
309 ir->clk = devm_clk_get(dev, "clk");
310 if (IS_ERR(ir->clk)) {
311 dev_err(dev, "failed to get a ir clock.\n");
312 return PTR_ERR(ir->clk);
315 ir->bus = devm_clk_get(dev, "bus");
316 if (IS_ERR(ir->bus)) {
319 * ir->bus uses the same clock as ir->clock.
321 ir->bus = ir->clk;
324 ir->base = devm_platform_ioremap_resource(pdev, 0);
325 if (IS_ERR(ir->base))
326 return PTR_ERR(ir->base);
328 ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
329 if (!ir->rc) {
334 ir->rc->priv = ir;
335 ir->rc->device_name = MTK_IR_DEV;
336 ir->rc->input_phys = MTK_IR_DEV "/input0";
337 ir->rc->input_id.bustype = BUS_HOST;
338 ir->rc->input_id.vendor = 0x0001;
339 ir->rc->input_id.product = 0x0001;
340 ir->rc->input_id.version = 0x0001;
342 ir->rc->map_name = map_name ?: RC_MAP_EMPTY;
343 ir->rc->dev.parent = dev;
344 ir->rc->driver_name = MTK_IR_DEV;
345 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
346 ir->rc->rx_resolution = MTK_IR_SAMPLE;
347 ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
349 ret = devm_rc_register_device(dev, ir->rc);
355 platform_set_drvdata(pdev, ir);
357 ir->irq = platform_get_irq(pdev, 0);
358 if (ir->irq < 0)
361 if (clk_prepare_enable(ir->clk)) {
366 if (clk_prepare_enable(ir->bus)) {
376 mtk_irq_disable(ir, MTK_IRINT_EN);
378 ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir);
387 val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) &
388 ir->data->fields[MTK_CHK_PERIOD].mask;
389 mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask,
390 ir->data->fields[MTK_CHK_PERIOD].reg);
396 val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) &
397 ir->data->fields[MTK_HW_PERIOD].mask;
398 mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask,
399 ir->data->fields[MTK_HW_PERIOD].reg);
402 mtk_w32_mask(ir, MTK_DG_CNT(1), MTK_DG_CNT_MASK, MTK_IRTHD);
405 val = mtk_r32(ir, MTK_CONFIG_HIGH_REG) & ~MTK_OK_COUNT_MASK;
406 val |= MTK_OK_COUNT(ir->data->ok_count) | MTK_PWM_EN | MTK_IR_EN;
407 mtk_w32(ir, val, MTK_CONFIG_HIGH_REG);
409 mtk_irq_enable(ir, MTK_IRINT_EN);
417 clk_disable_unprepare(ir->bus);
419 clk_disable_unprepare(ir->clk);
426 struct mtk_ir *ir = platform_get_drvdata(pdev);
433 mtk_irq_disable(ir, MTK_IRINT_EN);
434 synchronize_irq(ir->irq);
436 clk_disable_unprepare(ir->bus);
437 clk_disable_unprepare(ir->clk);