Lines Matching defs:data
37 /* Fields containing pulse width data */
70 /* Register containing pulse width data */
104 * @ok_count: The count indicating the completion of IR data
135 * @data: Holding specific data for vaious platform
144 const struct mtk_ir_data *data;
149 return ir->data->regs[MTK_CHKDATA_REG] + 4 * i;
161 USEC_PER_SEC * ir->data->div / MTK_IR_SAMPLE);
164 clk_get_rate(ir->bus) / ir->data->div);
193 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
194 mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]);
201 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
202 mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]);
261 mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]);
265 ir->data->regs[MTK_IRINT_CLR_REG]);
287 { .compatible = "mediatek,mt7623-cir", .data = &mt7623_data},
288 { .compatible = "mediatek,mt7622-cir", .data = &mt7622_data},
307 ir->data = of_device_get_match_data(dev);
387 val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) &
388 ir->data->fields[MTK_CHK_PERIOD].mask;
389 mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask,
390 ir->data->fields[MTK_CHK_PERIOD].reg);
396 val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) &
397 ir->data->fields[MTK_HW_PERIOD].mask;
398 mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask,
399 ir->data->fields[MTK_HW_PERIOD].reg);
406 val |= MTK_OK_COUNT(ir->data->ok_count) | MTK_PWM_EN | MTK_IR_EN;