Lines Matching defs:xvip
72 * @xvip: Xilinx Video IP device
89 struct xvip_device xvip;
112 return container_of(subdev, struct xtpg_device, xvip.subdev);
176 xvip_stop(&xtpg->xvip);
185 xvip_set_frame_size(&xtpg->xvip, &xtpg->formats[0]);
218 xvip_clr_and_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
238 xvip_write(&xtpg->xvip, XTPG_BAYER_PHASE, bayer_phase);
243 xvip_start(&xtpg->xvip);
259 return v4l2_subdev_get_try_format(&xtpg->xvip.subdev,
380 xvip_clr_and_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
384 xvip_clr_or_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
388 xvip_clr_or_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
392 xvip_clr_and_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
398 xvip_clr_or_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
402 xvip_clr_or_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
406 xvip_clr_or_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
410 xvip_write(&xtpg->xvip, XTPG_MOTION_SPEED, ctrl->val);
413 xvip_clr_and_set(&xtpg->xvip, XTPG_CROSS_HAIRS,
418 xvip_clr_and_set(&xtpg->xvip, XTPG_CROSS_HAIRS,
423 xvip_clr_and_set(&xtpg->xvip, XTPG_ZPLATE_HOR_CONTROL,
428 xvip_clr_and_set(&xtpg->xvip, XTPG_ZPLATE_HOR_CONTROL,
433 xvip_clr_and_set(&xtpg->xvip, XTPG_ZPLATE_VER_CONTROL,
438 xvip_clr_and_set(&xtpg->xvip, XTPG_ZPLATE_VER_CONTROL,
443 xvip_write(&xtpg->xvip, XTPG_BOX_SIZE, ctrl->val);
446 xvip_write(&xtpg->xvip, XTPG_BOX_COLOR, ctrl->val);
449 xvip_write(&xtpg->xvip, XTPG_STUCK_PIXEL_THRESH, ctrl->val);
452 xvip_write(&xtpg->xvip, XTPG_NOISE_GAIN, ctrl->val);
693 xvip_suspend(&xtpg->xvip);
702 xvip_resume(&xtpg->xvip);
713 struct device *dev = xtpg->xvip.dev;
714 struct device_node *node = xtpg->xvip.dev->of_node;
781 xtpg->xvip.dev = &pdev->dev;
787 ret = xvip_init_resources(&xtpg->xvip);
805 xvip_reset(&xtpg->xvip);
821 xvip_get_frame_size(&xtpg->xvip, &xtpg->default_format);
832 subdev = &xtpg->xvip.subdev;
878 xvip_print_version(&xtpg->xvip);
893 xvip_cleanup_resources(&xtpg->xvip);
900 struct v4l2_subdev *subdev = &xtpg->xvip.subdev;
906 xvip_cleanup_resources(&xtpg->xvip);